threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
55 lines
1.7 KiB
C
55 lines
1.7 KiB
C
/*
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* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 Memory Control register definitions
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*/
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#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
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#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
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#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
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#define S3C2410_BWSCON S3C2410_MEMREG(0x00)
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#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04)
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#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08)
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#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C)
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#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10)
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#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14)
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#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18)
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#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C)
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#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20)
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#define S3C2410_REFRESH S3C2410_MEMREG(0x24)
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#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28)
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#define S3C2410_BWSCON_ST1 (1 << 7)
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#define S3C2410_BWSCON_ST2 (1 << 11)
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#define S3C2410_BWSCON_ST3 (1 << 15)
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#define S3C2410_BWSCON_ST4 (1 << 19)
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#define S3C2410_BWSCON_ST5 (1 << 23)
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#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
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#define S3C2410_BWSCON_WS (1 << 2)
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#define S3C2410_BANKCON_PMC16 (0x3)
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#define S3C2410_BANKCON_Tacp_SHIFT (2)
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#define S3C2410_BANKCON_Tcah_SHIFT (4)
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#define S3C2410_BANKCON_Tcoh_SHIFT (6)
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#define S3C2410_BANKCON_Tacc_SHIFT (8)
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#define S3C2410_BANKCON_Tcos_SHIFT (11)
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#define S3C2410_BANKCON_Tacs_SHIFT (13)
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#define S3C2410_BANKCON_SDRAM (0x3 << 15)
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#define S3C2410_REFRESH_SELF (1 << 22)
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#define S3C2410_BANKSIZE_MASK (0x7 << 0)
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#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
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