threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
/*
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* arch/arm/mach-ks8695/include/mach/regs-sys.h
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*
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* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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* Copyright (C) 2006 Simtec Electronics
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*
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* KS8695 - System control registers and bit definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_SYS_H
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#define KS8695_SYS_H
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#define KS8695_SYS_OFFSET (0xF0000 + 0x0000)
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#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET)
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#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET)
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#define KS8695_SYSCFG (0x00) /* System Configuration Register */
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#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */
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/* System Configuration Register */
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#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */
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/* System Clock and Bus Control Register */
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#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */
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#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */
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#endif
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