threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
/*
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* arch/arm/mach-ks8695/include/mach/regs-pci.h
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*
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* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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* Copyright (C) 2006 Simtec Electronics
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*
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* KS8695 - PCI bridge registers and bit definitions.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
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#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET)
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#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET)
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#define KS8695_CRCFID (0x000) /* Configuration: Identification */
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#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
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#define KS8695_CRCFRV (0x008) /* Configuration: Revision */
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#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
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#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
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#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
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#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
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#define KS8695_PBCA (0x100) /* Bridge Configuration Address */
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#define KS8695_PBCD (0x104) /* Bridge Configuration Data */
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#define KS8695_PBM (0x200) /* Bridge Mode */
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#define KS8695_PBCS (0x204) /* Bridge Control and Status */
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#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
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#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
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#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
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#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
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#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */
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#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */
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#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */
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#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */
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/* Configuration: Identification */
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/* Configuration: Command and Status */
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/* Configuration: Revision */
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#define CFRV_GUEST (1 << 23)
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#define PBCA_TYPE1 (1)
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#define PBCA_ENABLE (1 << 31)
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