threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
109 lines
2.2 KiB
Devicetree
109 lines
2.2 KiB
Devicetree
/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx51-digi-connectcore-som.dtsi"
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/ {
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model = "Digi ConnectCore CC(W)-MX51 JSK";
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compatible = "digi,connectcore-ccxmx51-jsk",
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"digi,connectcore-ccxmx51-som", "fsl,imx51";
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chosen {
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linux,stdout-path = &uart1;
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};
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};
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&owire {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_owire>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usbotg {
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dr_mode = "otg";
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status = "okay";
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};
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&usbh1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1>;
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dr_mode = "host";
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phy_type = "ulpi";
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disable-over-current;
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status = "okay";
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};
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&iomuxc {
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imx51-digi-connectcore-jsk {
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pinctrl_owire: owiregrp {
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fsl,pins = <
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MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
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MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
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MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
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MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
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>;
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};
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pinctrl_usbh1: usbh1grp {
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fsl,pins = <
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MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
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MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
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MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
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MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
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MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
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MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
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MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
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MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
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MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
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MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
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MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
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MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
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>;
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};
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};
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};
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