threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
178 lines
3.2 KiB
C
178 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ALPHA_SPINLOCK_H
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#define _ALPHA_SPINLOCK_H
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#include <linux/kernel.h>
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#include <asm/current.h>
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#include <asm/barrier.h>
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#include <asm/processor.h>
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.lock == 0;
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}
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static inline void arch_spin_unlock(arch_spinlock_t * lock)
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{
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mb();
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lock->lock = 0;
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}
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static inline void arch_spin_lock(arch_spinlock_t * lock)
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{
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long tmp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" bne %0,2f\n"
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" lda %0,1\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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" mb\n"
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".subsection 2\n"
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"2: ldl %0,%1\n"
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" bne %0,2b\n"
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" br 1b\n"
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".previous"
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: "=&r" (tmp), "=m" (lock->lock)
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: "m"(lock->lock) : "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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return !test_and_set_bit(0, &lock->lock);
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}
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/***********************************************************/
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static inline int arch_read_can_lock(arch_rwlock_t *lock)
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{
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return (lock->lock & 1) == 0;
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}
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static inline int arch_write_can_lock(arch_rwlock_t *lock)
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{
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return lock->lock == 0;
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}
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static inline void arch_read_lock(arch_rwlock_t *lock)
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{
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long regx;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" blbs %1,6f\n"
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" subl %1,2,%1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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" mb\n"
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".subsection 2\n"
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"6: ldl %1,%0\n"
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" blbs %1,6b\n"
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" br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline void arch_write_lock(arch_rwlock_t *lock)
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{
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long regx;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" bne %1,6f\n"
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" lda %1,1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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" mb\n"
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".subsection 2\n"
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"6: ldl %1,%0\n"
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" bne %1,6b\n"
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" br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t * lock)
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{
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long regx;
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int success;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" lda %2,0\n"
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" blbs %1,2f\n"
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" subl %1,2,%2\n"
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" stl_c %2,%0\n"
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" beq %2,6f\n"
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"2: mb\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx), "=&r" (success)
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: "m" (*lock) : "memory");
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return success;
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}
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static inline int arch_write_trylock(arch_rwlock_t * lock)
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{
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long regx;
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int success;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" lda %2,0\n"
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" bne %1,2f\n"
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" lda %2,1\n"
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" stl_c %2,%0\n"
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" beq %2,6f\n"
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"2: mb\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx), "=&r" (success)
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: "m" (*lock) : "memory");
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return success;
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}
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static inline void arch_read_unlock(arch_rwlock_t * lock)
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{
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long regx;
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__asm__ __volatile__(
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" mb\n"
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"1: ldl_l %1,%0\n"
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" addl %1,2,%1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline void arch_write_unlock(arch_rwlock_t * lock)
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{
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mb();
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lock->lock = 0;
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}
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#endif /* _ALPHA_SPINLOCK_H */
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