threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.2 KiB
Plaintext
37 lines
1.2 KiB
Plaintext
Kernel driver w1_ds28e04
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========================
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Supported chips:
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* Maxim DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO
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supported family codes:
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W1_FAMILY_DS28E04 0x1C
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Author: Markus Franke, <franke.m@sebakmt.com> <franm@hrz.tu-chemnitz.de>
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Description
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-----------
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Support is provided through the sysfs files "eeprom" and "pio". CRC checking
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during memory accesses can optionally be enabled/disabled via the device
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attribute "crccheck". The strong pull-up can optionally be enabled/disabled
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via the module parameter "w1_strong_pullup".
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Memory Access
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A read operation on the "eeprom" file reads the given amount of bytes
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from the EEPROM of the DS28E04.
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A write operation on the "eeprom" file writes the given byte sequence
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to the EEPROM of the DS28E04. If CRC checking mode is enabled only
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fully aligned blocks of 32 bytes with valid CRC16 values (in bytes 30
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and 31) are allowed to be written.
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PIO Access
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The 2 PIOs of the DS28E04-100 are accessible via the "pio" sysfs file.
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The current status of the PIO's is returned as an 8 bit value. Bit 0/1
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represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are
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driven low-active, i.e. the driver delivers/expects low-active values.
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