threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
49 lines
1.5 KiB
Plaintext
49 lines
1.5 KiB
Plaintext
Texas Instruments TAS5086 6-channel PWM Processor
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Required properties:
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- compatible: Should contain "ti,tas5086".
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- reg: The i2c address. Should contain <0x1b>.
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Optional properties:
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- reset-gpio: A GPIO spec to define which pin is connected to the
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chip's !RESET pin. If specified, the driver will
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assert a hardware reset at probe time.
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- ti,charge-period: This property should contain the time in microseconds
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that closely matches the external single-ended
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split-capacitor charge period. The hardware chip
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waits for this period of time before starting the
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PWM signals. This helps reduce pops and clicks.
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When not specified, the hardware default of 1300ms
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is retained.
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- ti,mid-z-channel-X: Boolean properties, X being a number from 1 to 6.
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If given, channel X will start with the Mid-Z start
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sequence, otherwise the default Low-Z scheme is used.
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The correct configuration depends on how the power
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stages connected to the PWM output pins work. Not all
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power stages are compatible to Mid-Z - please refer
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to the datasheets for more details.
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Most systems should not set any of these properties.
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- avdd-supply: Power supply for AVDD, providing 3.3V
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- dvdd-supply: Power supply for DVDD, providing 3.3V
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Examples:
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i2c_bus {
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tas5086@1b {
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compatible = "ti,tas5086";
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reg = <0x1b>;
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reset-gpio = <&gpio 23 0>;
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ti,charge-period = <156000>;
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avdd-supply = <&vdd_3v3_reg>;
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dvdd-supply = <&vdd_3v3_reg>;
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};
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};
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