threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
Texas Instruments - tas2552 Codec module
|
|
|
|
The tas2552 serial control bus communicates through I2C protocols
|
|
|
|
Required properties:
|
|
- compatible - One of:
|
|
"ti,tas2552" - TAS2552
|
|
- reg - I2C slave address: it can be 0x40 if ADDR pin is 0
|
|
or 0x41 if ADDR pin is 1.
|
|
- supply-*: Required supply regulators are:
|
|
"vbat" battery voltage
|
|
"iovdd" I/O Voltage
|
|
"avdd" Analog DAC Voltage
|
|
|
|
Optional properties:
|
|
- enable-gpio - gpio pin to enable/disable the device
|
|
|
|
tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
|
|
internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
|
|
reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
|
|
For system integration the dt-bindings/sound/tas2552.h header file provides
|
|
defined values to select and configure the PLL and PDM reference clocks.
|
|
|
|
Example:
|
|
|
|
tas2552: tas2552@41 {
|
|
compatible = "ti,tas2552";
|
|
reg = <0x41>;
|
|
vbat-supply = <®_vbat>;
|
|
iovdd-supply = <®_iovdd>;
|
|
avdd-supply = <®_avdd>;
|
|
enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
For more product information please see the link below:
|
|
http://www.ti.com/product/TAS2552
|