threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
57 lines
1.7 KiB
Plaintext
57 lines
1.7 KiB
Plaintext
Device Tree bindings for Marvell PMU
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Required properties:
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- compatible: value should be "marvell,dove-pmu".
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May also include "simple-bus" if there are child devices, in which
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case the ranges node is required.
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- reg: two base addresses and sizes of the PM controller and PMU.
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- interrupts: single interrupt number for the PMU interrupt
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- interrupt-controller: must be specified as the PMU itself is an
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interrupt controller.
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- #interrupt-cells: must be 1.
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- #reset-cells: must be 1.
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- domains: sub-node containing domain descriptions
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Optional properties:
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- ranges: defines the address mapping for child devices, as per the
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standard property of this name. Required when compatible includes
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"simple-bus".
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Power domain descriptions are listed as child nodes of the "domains"
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sub-node. Each domain has the following properties:
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Required properties:
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- #power-domain-cells: must be 0.
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Optional properties:
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- marvell,pmu_pwr_mask: specifies the mask value for PMU power register
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- marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
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- resets: points to the reset manager (PMU node) and reset index.
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Example:
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pmu: power-management@d0000 {
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compatible = "marvell,dove-pmu";
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reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
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interrupts = <33>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#reset-cells = <1>;
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domains {
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vpu_domain: vpu-domain {
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#power-domain-cells = <0>;
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marvell,pmu_pwr_mask = <0x00000008>;
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marvell,pmu_iso_mask = <0x00000001>;
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resets = <&pmu 16>;
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};
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gpu_domain: gpu-domain {
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#power-domain-cells = <0>;
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marvell,pmu_pwr_mask = <0x00000004>;
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marvell,pmu_iso_mask = <0x00000002>;
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resets = <&pmu 18>;
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};
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};
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};
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