threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
43 lines
1.3 KiB
Plaintext
43 lines
1.3 KiB
Plaintext
CSR SiRFSoC Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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example:
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rstc: reset-controller@88010000 {
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compatible = "sirf,prima2-rstc";
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reg = <0x88010000 0x1000>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The reset controller(rstc) manages various reset sources. This module provides
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reset signals for most blocks in system. Those device nodes should specify the
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reset line on the rstc in their resets property, containing a phandle to the
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rstc device node and a RESET_INDEX specifying which module to reset, as described
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in reset.txt.
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For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
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For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
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rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
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example:
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vpp@90020000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x90020000 0x10000>;
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interrupts = <31>;
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clocks = <&clks 35>;
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resets = <&rstc 6>;
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};
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