threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
85 lines
2.8 KiB
Plaintext
85 lines
2.8 KiB
Plaintext
* ZTE ZX Pin Controller
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The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of
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a main controller and an auxiliary one. For example, on ZX296718 SoC, the
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main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
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controllers work together to control pin multiplexing and configuration in
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the way illustrated as below.
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GMII_RXD3 ---+
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DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
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BGPIO16 ---+ ^
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| pinconf
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^ |
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| pinmux |
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TOP_PMM (main) AON_IOCFG (aux)
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| pinmux | |
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| pinmux v |
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v | pinconf
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KEY_ROW2 ---+ v
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PORT1_LCD_TE ---+ |
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| AGPIO10 ---+------ KEY_ROW2 (AON pin)
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I2S0_DOUT3 ---+ |
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|-----------------------+
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PWM_OUT3 ---+
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VGA_VS1 ---+
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For most of pins like GMII_RXD3 in the figure, the pinmux function is
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controlled by TOP_PMM block only, and this type of pins are meant by term
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'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
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TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
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the pin spread in both controllers. This type of pins are called 'AON pins'.
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Though pinmux implementation is quite different, pinconf is same for both
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types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
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on ZX296718.
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Required properties:
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- compatible: should be "zte,zx296718-pmm".
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- reg: the register physical address and length.
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- zte,auxiliary-controller: phandle to the auxiliary pin controller which
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implements pinmux for AON pins and pinconf for all pins.
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The following pin configuration are supported. Please refer to
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pinctrl-bindings.txt in this directory for more details of the common
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pinctrl bindings used by client devices.
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- bias-pull-up
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- bias-pull-down
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- drive-strength
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- input-enable
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- slew-rate
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Examples:
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iocfg: pin-controller@119000 {
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compatible = "zte,zx296718-iocfg";
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reg = <0x119000 0x1000>;
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};
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pmm: pin-controller@1462000 {
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compatible = "zte,zx296718-pmm";
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reg = <0x1462000 0x1000>;
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zte,auxiliary-controller = <&iocfg>;
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};
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&pmm {
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vga_pins: vga {
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pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
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function = "VGA";
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};
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};
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&vga {
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pinctrl-names = "default";
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pinctrl-0 = <&vga_pins>;
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};
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