threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
Ingenic jz47xx pin controller
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
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be used as GPIOs, multiplexed device functions are configured within the
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GPIO port configuration registers and it is typical to refer to pins using the
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naming scheme "PxN" where x is a character identifying the GPIO port with
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which the pin is associated and N is an integer from 0 to 31 identifying the
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pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
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PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
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PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
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total of 192 pins.
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Required properties:
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--------------------
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- compatible: One of:
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- "ingenic,jz4740-pinctrl"
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- "ingenic,jz4770-pinctrl"
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- "ingenic,jz4780-pinctrl"
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- reg: Address range of the pinctrl registers.
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GPIO sub-nodes
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--------------
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The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
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please refer to ../gpio/ingenic,gpio.txt.
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Example:
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--------
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pinctrl: pin-controller@10010000 {
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compatible = "ingenic,jz4740-pinctrl";
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reg = <0x10010000 0x400>;
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};
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