threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
89 lines
2.7 KiB
Plaintext
89 lines
2.7 KiB
Plaintext
* Xilinx AXI PCIe Root Port Bridge DT description
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Required properties:
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
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- reg: Should contain AXI PCIe registers location and length
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- device_type: must be "pci"
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- interrupts: Should contain AXI PCIe interrupt
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- interrupt-map-mask,
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interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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- ranges: ranges for the PCI memory regions (I/O space region is not
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supported by hardware)
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Please refer to the standard PCI bus binding document for a more
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detailed explanation
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Optional properties for Zynq/Microblaze:
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- bus-range: PCI bus numbers covered
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Interrupt controller child node
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+++++++++++++++++++++++++++++++
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Required properties:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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NOTE:
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The core provides a single interrupt for both INTx/MSI messages. So,
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created a interrupt controller node to support 'interrupt-map' DT
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functionality. The driver will create an IRQ domain for this map, decode
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the four INTx interrupts in ISR and route them to this domain.
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Example:
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++++++++
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Zynq:
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pci_express: axi-pcie@50000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = < 0x50000000 0x1000000 >;
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device_type = "pci";
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interrupts = < 0 52 4 >;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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Microblaze:
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pci_express: axi-pcie@10000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = <0x10000000 0x4000000>;
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device_type = "pci";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = <1 2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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