threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
44 lines
1.3 KiB
Plaintext
44 lines
1.3 KiB
Plaintext
* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)
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Required properties:
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- compatible: should be "st,stm32f469-qspi"
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- reg: the first contains the register location and length.
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the second contains the memory mapping address and length
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- reg-names: should contain the reg names "qspi" "qspi_mm"
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- interrupts: should contain the interrupt for the device
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- clocks: the phandle of the clock needed by the QSPI controller
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- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
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Optional properties:
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- resets: must contain the phandle to the reset controller.
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A spi flash must be a child of the nor_flash node and could have some
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properties. Also see jedec,spi-nor.txt.
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Required properties:
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- reg: chip-Select number (QSPI controller may connect 2 nor flashes)
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- spi-max-frequency: max frequency of spi bus
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Optional property:
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- spi-rx-bus-width: see ../spi/spi-bus.txt for the description
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Example:
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qspi: spi@a0001000 {
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compatible = "st,stm32f469-qspi";
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reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <91>;
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resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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flash@0 {
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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...
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};
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};
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