threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
42 lines
1.5 KiB
Plaintext
42 lines
1.5 KiB
Plaintext
* Freescale Quad Serial Peripheral Interface(QuadSPI)
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Required properties:
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- compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
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"fsl,imx7d-qspi", "fsl,imx6ul-qspi",
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"fsl,ls1021a-qspi"
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or
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"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
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"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
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- interrupts : Should contain the interrupt for the device
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- clocks : The clocks needed by the QuadSPI controller
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- clock-names : the name of the clocks
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Optional properties:
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- fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
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Each bus can be connected with two NOR flashes.
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Most of the time, each bus only has one NOR flash
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connected, this is the default case.
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But if there are two NOR flashes connected to the
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bus, you should enable this property.
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(Please check the board's schematic.)
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- big-endian : That means the IP register is big endian
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Example:
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qspi0: quadspi@40044000 {
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compatible = "fsl,vf610-qspi";
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reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_QSPI0_EN>,
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<&clks VF610_CLK_QSPI0>;
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clock-names = "qspi_en", "qspi";
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flash0: s25fl128s@0 {
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....
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};
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};
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