threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.2 KiB
Plaintext
37 lines
1.2 KiB
Plaintext
Lantiq XWAY SoC GPHY binding
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============================
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This binding describes a software-defined ethernet PHY, provided by the RCU
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module on newer Lantiq XWAY SoCs (xRX200 and newer).
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,xrx200a1x-gphy"
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"lantiq,xrx200a2x-gphy"
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"lantiq,xrx300-gphy"
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"lantiq,xrx330-gphy"
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- reg : Addrress of the GPHY FW load address register
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- resets : Must reference the RCU GPHY reset bit
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- reset-names : One entry, value must be "gphy" or optional "gphy2"
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- clocks : A reference to the (PMU) GPHY clock gate
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Optional properties:
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- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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<dt-bindings/mips/lantiq_xway_gphy.h>
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-------------------------------------------------------------------------------
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Example for the GPHys on the xRX200 SoCs:
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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