threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
44 lines
1.1 KiB
Plaintext
44 lines
1.1 KiB
Plaintext
* Cavium Interrupt Bus widget
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Properties:
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- compatible: "cavium,octeon-7130-cib"
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Compatibility with cn70XX SoCs.
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- interrupt-controller: This is an interrupt controller.
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- reg: Two elements consisting of the addresses of the RAW and EN
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registers of the CIB block
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- cavium,max-bits: The index (zero based) of the highest numbered bit
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in the CIB block.
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- interrupt-parent: Always the CIU on the SoC.
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- interrupts: The CIU line to which the CIB block is connected.
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- #interrupt-cells: Must be <2>. The first cell is the bit within the
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CIB. The second cell specifies the triggering semantics of the
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line.
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Example:
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interrupt-controller@107000000e000 {
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compatible = "cavium,octeon-7130-cib";
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reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
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<0x10700 0x0000e100 0x0 0x8>; /* EN */
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cavium,max-bits = <23>;
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interrupt-controller;
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interrupt-parent = <&ciu>;
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interrupts = <1 24>;
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/* Interrupts are specified by two parts:
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* 1) Bit number in the CIB* registers
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* 2) Triggering (1 - edge rising
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* 2 - edge falling
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* 4 - level active high
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* 8 - level active low)
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*/
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#interrupt-cells = <2>;
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};
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