threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
56 lines
1.4 KiB
Plaintext
56 lines
1.4 KiB
Plaintext
Xilinx Video IP Pipeline (VIPP)
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-------------------------------
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General concept
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---------------
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Xilinx video IP pipeline processes video streams through one or more Xilinx
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video IP cores. Each video IP core is represented as documented in video.txt
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and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
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node of the VIPP represents as a top level node of the pipeline and defines
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mappings between DMAs and the video IP cores.
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Required properties:
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- compatible: Must be "xlnx,video".
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- dmas, dma-names: List of one DMA specifier and identifier string (as defined
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in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
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requires a DMA channel with the identifier string set to "port" followed by
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the port index.
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- ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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Required port properties:
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- direction: should be either "input" or "output" depending on the direction
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of stream.
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Example:
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video_cap {
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compatible = "xlnx,video";
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dmas = <&vdma_1 1>, <&vdma_3 1>;
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dma-names = "port0", "port1";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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direction = "input";
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vcap0_in0: endpoint {
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remote-endpoint = <&scaler0_out>;
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};
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};
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port@1 {
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reg = <1>;
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direction = "input";
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vcap0_in1: endpoint {
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remote-endpoint = <&switch_out1>;
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};
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};
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};
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};
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