threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
38 lines
1.4 KiB
Plaintext
38 lines
1.4 KiB
Plaintext
* Mediatek JPEG Decoder
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Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
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Required properties:
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- compatible : must be one of the following string:
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"mediatek,mt8173-jpgdec"
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"mediatek,mt2701-jpgdec"
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- reg : physical base address of the jpeg decoder registers and length of
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memory mapped region.
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- interrupts : interrupt number to the interrupt controller.
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- clocks: device clocks, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: must contain "jpgdec-smi" and "jpgdec".
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- power-domains: a phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details.
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- mediatek,larb: must contain the local arbiters in the current Socs, see
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Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
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for details.
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- iommus: should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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for details.
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Example:
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt2701-jpgdec";
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reg = <0 0x15004000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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