threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
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On most SoC the IRQ controller need to flush the DDR FIFO before running
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the interrupt handler of some devices. This is configured using the
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qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
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Required Properties:
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- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
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as fallback
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source, should be 1 for intc
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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Optional Properties:
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- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
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buffer flush
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- qca,ddr-wb-channels: List of phandles to the write buffer channels for
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each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
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default to the entry's index.
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Example:
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interrupt-controller {
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compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
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qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
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<&ddr_ctrl 0>, <&ddr_ctrl 1>;
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};
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...
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ddr_ctrl: memory-controller@18000000 {
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...
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#qca,ddr-wb-channel-cells = <1>;
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};
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