threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
Altera FPGA/HPS Bridge Driver
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Required properties:
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- regs : base address and size for AXI bridge module
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- compatible : Should contain one of:
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"altr,socfpga-lwhps2fpga-bridge",
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"altr,socfpga-hps2fpga-bridge", or
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"altr,socfpga-fpga2hps-bridge"
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- resets : Phandle and reset specifier for this bridge's reset
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- clocks : Clocks used by this module.
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Optional properties:
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- bridge-enable : 0 if driver should disable bridge at startup.
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1 if driver should enable bridge at startup.
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Default is to leave bridge in its current state.
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Example:
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fpga_bridge0: fpga-bridge@ff400000 {
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compatible = "altr,socfpga-lwhps2fpga-bridge";
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reg = <0xff400000 0x100000>;
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resets = <&rst LWHPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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bridge-enable = <0>;
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};
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fpga_bridge1: fpga-bridge@ff500000 {
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compatible = "altr,socfpga-hps2fpga-bridge";
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reg = <0xff500000 0x10000>;
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resets = <&rst HPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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bridge-enable = <1>;
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};
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fpga_bridge2: fpga-bridge@ff600000 {
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compatible = "altr,socfpga-fpga2hps-bridge";
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reg = <0xff600000 0x100000>;
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resets = <&rst FPGA2HPS_RESET>;
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clocks = <&l4_main_clk>;
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};
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