threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
* Renesas R8A73A4 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
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and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,r8a73a4-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
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"m1", "m2", "zx", "zs", and "hp".
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a73a4-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll2s", "pll2h", "z", "z2",
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"i", "m3", "b", "m1", "m2",
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"zx", "zs", "hp";
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};
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