threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
22 lines
743 B
Plaintext
22 lines
743 B
Plaintext
* Marvell PXA910 Clock Controller
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The PXA910 clock subsystem generates and supplies clock to various
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controllers within the PXA910 SoC.
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Required Properties:
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- compatible: should be one of the following.
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- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
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- reg: physical base address of the clock subsystem and length of memory mapped
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region. There are 4 places in SOC has clock control logic:
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"mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
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