threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
32 lines
986 B
Plaintext
32 lines
986 B
Plaintext
Device Tree Clock bindings for Marvell Berlin
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Clock related registers are spread among the chip control registers. Berlin
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clock node should be a sub-node of the chip controller node. Marvell Berlin2
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(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
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minor differences in features and register layout.
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Required properties:
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- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
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- #clock-cells: must be 1
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- clocks: must be the input parent clock phandle
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- clock-names: name of the input parent clock
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Allowed clock-names for the reference clocks are
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"refclk" for the SoCs oscillator input on all SoCs,
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and SoC-specific input clocks for
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BG2/BG2CD: "video_ext0" for the external video clock input
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Example:
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chip_clk: clock {
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compatible = "marvell,berlin2q-clk";
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#clock-cells = <1>;
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clocks = <&refclk>;
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clock-names = "refclk";
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};
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