threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
54 lines
1.3 KiB
Plaintext
54 lines
1.3 KiB
Plaintext
Ingenic SoC CGU binding
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The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
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typically includes a variety of PLLs, multiplexers, dividers & gates in order
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to provide many different clock signals derived from only 2 external source
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clocks.
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Required properties:
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- compatible : Should be "ingenic,<soctype>-cgu".
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For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
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- reg : The address & length of the CGU registers.
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- clocks : List of phandle & clock specifiers for clocks external to the CGU.
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Two such external clocks should be specified - first the external crystal
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"ext" and second the RTC clock source "rtc".
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- clock-names : List of name strings for the external clocks.
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- #clock-cells: Should be 1.
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Clock consumers specify this argument to identify a clock. The valid values
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may be found in <dt-bindings/clock/<soctype>-cgu.h>.
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Example SoC include file:
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/ {
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cgu: jz4740-cgu {
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compatible = "ingenic,jz4740-cgu";
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reg = <0x10000000 0x100>;
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#clock-cells = <1>;
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};
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uart0: serial@10030000 {
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clocks = <&cgu JZ4740_CLK_UART0>;
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};
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};
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Example board file:
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/ {
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ext: clock@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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rtc: clock@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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&cgu {
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clocks = <&ext> <&rtc>;
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clock-names: "ext", "rtc";
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};
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};
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