threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
* Clock bindings for Axis ARTPEC-6 chip
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The bindings are based on the clock provider binding in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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External clocks:
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----------------
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There are two external inputs to the main clock controller which should be
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provided using the common clock bindings.
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- "sys_refclk": External 50 Mhz oscillator (required)
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- "i2s_refclk": Alternate audio reference clock (optional).
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Main clock controller
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---------------------
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Required properties:
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- #clock-cells: Should be <1>
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See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
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- compatible: Should be "axis,artpec6-clkctrl"
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- reg: Must contain the base address and length of the system controller
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- clocks: Must contain a phandle entry for each clock in clock-names
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- clock-names: Must include the external oscillator ("sys_refclk"). Optional
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ones are the audio reference clock ("i2s_refclk") and the audio fractional
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dividers ("frac_clk0" and "frac_clk1").
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Examples:
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ext_clk: ext_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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clkctrl: clkctrl@f8000000 {
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#clock-cells = <1>;
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compatible = "axis,artpec6-clkctrl";
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reg = <0xf8000000 0x48>;
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clocks = <&ext_clk>;
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clock-names = "sys_refclk";
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};
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