threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
41 lines
1.0 KiB
Plaintext
41 lines
1.0 KiB
Plaintext
C6X PLL Clock Controllers
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-------------------------
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This is a first-cut support for the SoC clock controllers. This is still
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under development and will probably change as the common device tree
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clock support is added to the kernel.
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Required properties:
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- compatible: "ti,c64x+pll"
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May also have SoC-specific value to support SoC-specific initialization
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in the driver. One of:
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"ti,c6455-pll"
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"ti,c6457-pll"
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"ti,c6472-pll"
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"ti,c6474-pll"
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- reg: base address and size of register area
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- clock-frequency: input clock frequency in hz
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Optional properties:
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- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
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- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
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- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
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Example:
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clock-controller@29a0000 {
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compatible = "ti,c6472-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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clock-frequency = <25000000>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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