threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
52 lines
2.0 KiB
Plaintext
52 lines
2.0 KiB
Plaintext
MediaTek Serial ATA controller
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Required properties:
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- compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
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When using "mediatek,mtk-ahci" compatible strings, you
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need SoC specific ones in addition, one of:
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- "mediatek,mt7622-ahci"
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- reg : Physical base addresses and length of register sets.
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- interrupts : Interrupt associated with the SATA device.
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- interrupt-names : Associated name must be: "hostc".
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- clocks : A list of phandle and clock specifier pairs, one for each
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entry in clock-names.
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- clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
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- phys : A phandle and PHY specifier pair for the PHY port.
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- phy-names : Associated name must be: "sata-phy".
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- ports-implemented : See ./ahci-platform.txt for details.
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Optional properties:
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- power-domains : A phandle and power domain specifier pair to the power
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domain which is responsible for collapsing and restoring
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power to the peripheral.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Associated names must be: "axi", "sw", "reg".
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- mediatek,phy-mode : A phandle to the system controller, used to enable
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SATA function.
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Example:
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sata: sata@1a200000 {
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compatible = "mediatek,mt7622-ahci",
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"mediatek,mtk-ahci";
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reg = <0 0x1a200000 0 0x1100>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hostc";
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clocks = <&pciesys CLK_SATA_AHB_EN>,
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<&pciesys CLK_SATA_AXI_EN>,
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<&pciesys CLK_SATA_ASIC_EN>,
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<&pciesys CLK_SATA_RBC_EN>,
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<&pciesys CLK_SATA_PM_EN>;
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clock-names = "ahb", "axi", "asic", "rbc", "pm";
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phys = <&u3port1 PHY_TYPE_SATA>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
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<&pciesys MT7622_SATA_PHY_SW_RST>,
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<&pciesys MT7622_SATA_PHY_REG_RST>;
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reset-names = "axi", "sw", "reg";
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mediatek,phy-mode = <&pciesys>;
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};
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