threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
284 lines
14 KiB
JSON
284 lines
14 KiB
JSON
[
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{
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"EventCode": "0x08",
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"UMask": "0x1",
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"BriefDescription": "Load misses in all DTLB levels that cause page walks",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
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"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x2",
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"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
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"PublicDescription": "Counts demand data loads that caused a completed page walk (4K page size). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x4",
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"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
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"PublicDescription": "Counts demand data loads that caused a completed page walk (2M and 4M page sizes). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x8",
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"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
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"PublicDescription": "Counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0xe",
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"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x10",
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"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
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"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture. ",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x10",
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"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
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"CounterMask": "1",
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"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x08",
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"UMask": "0x20",
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"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
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"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x1",
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"BriefDescription": "Store misses in all DTLB levels that cause page walks",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
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"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x2",
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"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
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"PublicDescription": "Counts demand data stores that caused a completed page walk (4K page size). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x4",
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"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
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"PublicDescription": "Counts demand data stores that caused a completed page walk (2M and 4M page sizes). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x8",
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"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
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"PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0xe",
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"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
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"PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x10",
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"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
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"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture. ",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x10",
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"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
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"CounterMask": "1",
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"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x49",
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"UMask": "0x20",
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"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
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"Counter": "0,1,2,3",
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"EventName": "DTLB_STORE_MISSES.STLB_HIT",
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"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x4F",
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"UMask": "0x10",
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"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
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"Counter": "0,1,2,3",
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"EventName": "EPT.WALK_PENDING",
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"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x1",
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"BriefDescription": "Misses at all ITLB levels that cause page walks",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
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"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x2",
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"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
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"PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x4",
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"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
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"PublicDescription": "Counts completed page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x8",
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"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
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"PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0xe",
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"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x10",
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"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_PENDING",
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"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture. ",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x10",
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"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.WALK_ACTIVE",
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"CounterMask": "1",
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"PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x85",
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"UMask": "0x20",
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"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
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"Counter": "0,1,2,3",
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"EventName": "ITLB_MISSES.STLB_HIT",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xAE",
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"UMask": "0x1",
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"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
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"Counter": "0,1,2,3",
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"EventName": "ITLB.ITLB_FLUSH",
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"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xBD",
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"UMask": "0x1",
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"BriefDescription": "DTLB flush attempts of the thread-specific entries",
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"Counter": "0,1,2,3",
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"EventName": "TLB_FLUSH.DTLB_THREAD",
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"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xBD",
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"UMask": "0x20",
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"BriefDescription": "STLB flush attempts",
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"Counter": "0,1,2,3",
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"EventName": "TLB_FLUSH.STLB_ANY",
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"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |