threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
307 lines
8.0 KiB
C
307 lines
8.0 KiB
C
/*
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* Copyright (C) 2018, SI-IN, Yun Shi (yun.shi@si-in.com).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//#define DEBUG
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#define LOG_FLAG "sia8159_regs"
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "sia81xx_common.h"
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#include "sia81xx_regmap.h"
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#include "sia8159_regs.h"
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#define SIA8159_WRITEABLE_REG_NUM (10)
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static const char sia8159_palyback_defaults[][SIA8159_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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},
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[SIA81XX_CHANNEL_R] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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}
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};
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static const char sia8159_voice_defaults[][SIA8159_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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},
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[SIA81XX_CHANNEL_R] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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}
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};
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static const char sia8159_receiver_defaults[][SIA8159_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0xAB, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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},
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[SIA81XX_CHANNEL_R] = {
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0xAB, //SIA8159_REG_SYSCTRL
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0x20, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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}
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};
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static const char sia8159_factory_defaults[][SIA8159_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x27, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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},
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[SIA81XX_CHANNEL_R] = {
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0xBD, //SIA8159_REG_SYSCTRL
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0x27, //SIA8159_REG_ALGO_EN
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0xAE, //SIA8159_REG_BST_CFG
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0xC9, //SIA8159_REG_CLSD_CFG
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0x00, //SIA8159_REG_ALGO_CFG1
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0x28, //SIA8159_REG_ALGO_CFG2
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0x73, //SIA8159_REG_ALGO_CFG3
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0x88, //SIA8159_REG_ALGO_CFG4
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0x0D, //SIA8159_REG_ALGO_CFG5
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0xA4 //SIA8159_REG_CLSD_OCPCFG
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}
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};
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const struct sia81xx_reg_default_val sia8159_reg_default_val = {
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.chip_type = CHIP_TYPE_SIA8159,
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.offset = SIA8159_REG_SYSCTRL,
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.reg_defaults[AUDIO_SCENE_PLAYBACK] = {
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.vals = (char *)sia8159_palyback_defaults,
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.num = ARRAY_SIZE(sia8159_palyback_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_VOICE] = {
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.vals = (char *)sia8159_voice_defaults,
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.num = ARRAY_SIZE(sia8159_voice_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_RECEIVER] = {
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.vals = (char *)sia8159_receiver_defaults,
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.num = ARRAY_SIZE(sia8159_receiver_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_FACTORY] = {
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.vals = (char *)sia8159_factory_defaults,
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.num = ARRAY_SIZE(sia8159_factory_defaults[0])
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}
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};
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static const SIA_CHIP_ID_RANGE chip_id_ranges[] = {
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{0x58, 0x58},
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{0x60, 0x68},
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{0x6A, 0x6F}
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};
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static bool sia8159_writeable_register(
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struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case SIA8159_REG_CHIP_ID ... 0x22 :
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return true;
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default :
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break;
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}
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return false;
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}
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static bool sia8159_readable_register(
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struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case SIA8159_REG_CHIP_ID ... 0x22 :
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case 0x41 :
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return true;
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default :
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break;
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}
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return false;
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}
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static bool sia8159_volatile_register(
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struct device *dev,
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unsigned int reg)
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{
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return true;
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}
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const struct regmap_config sia8159_regmap_config = {
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.name = "sia8159",
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.reg_bits = 8,
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.val_bits = 8,
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.reg_stride = 0,
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.pad_bits = 0,
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.cache_type = REGCACHE_NONE,
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.reg_defaults = NULL,
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.num_reg_defaults = 0,
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.writeable_reg = sia8159_writeable_register,
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.readable_reg = sia8159_readable_register,
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.volatile_reg = sia8159_volatile_register,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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};
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static int sia8159_check_chip_id(
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struct regmap *regmap)
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{
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char val = 0;
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int i = 0;
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if (0 != sia81xx_regmap_read(regmap, SIA8159_REG_CHIP_ID, 1, &val))
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return -1;
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for (i = 0; i < ARRAY_SIZE(chip_id_ranges); i++) {
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if (val >= chip_id_ranges[i].begin && val <= chip_id_ranges[i].end)
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return 0;
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}
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return -1;
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}
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static void sia8159_chip_on(
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struct regmap *regmap, unsigned int scene)
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{
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char val = 0;
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if (0 != sia81xx_regmap_read(regmap, SIA8159_REG_ALGO_CFG1, 1, &val))
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return;
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val |= 0x01;
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if (0 != sia81xx_regmap_write(regmap, SIA8159_REG_ALGO_CFG1, 1, &val))
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return;
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}
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static void sia8159_chip_off(
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struct regmap *regmap)
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{
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char val = 0;
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if (0 != sia81xx_regmap_write(regmap, SIA8159_REG_ALGO_CFG1, 1, &val))
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return;
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val = 0x41;
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if (0 != sia81xx_regmap_write(regmap, SIA8159_REG_SYSCTRL, 1, &val))
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return;
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val = 0x20;
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if (0 != sia81xx_regmap_write(regmap, SIA8159_REG_ALGO_EN, 1, &val))
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return;
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mdelay(1); // wait chip power off
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}
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static void sia8159_check_trimming(
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struct regmap *regmap)
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{
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enum { reg_num =
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SIA8159_REG_TRIMMING_END - SIA8159_REG_TRIMMING_BEGIN + 1 };
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static const char defaults[reg_num] = {0x76, 0x66, 0x70};
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uint8_t vals[reg_num];
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uint8_t crc = 0;
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/* wait reading trimming data to reg */
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mdelay(1);
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if (0 != sia81xx_regmap_read(regmap,
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SIA8159_REG_TRIMMING_BEGIN, reg_num, (char *)vals))
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return ;
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crc = vals[reg_num - 1] & 0x0F;
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vals[reg_num - 1] &= 0xF0;
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if (crc != crc4_itu(vals, reg_num)) {
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pr_warn("[ warn][%s] %s: trimming failed !! \r\n",
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LOG_FLAG, __func__);
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if (0 != sia81xx_regmap_read(regmap, SIA8159_REG_ALGO_CFG2, 1, (char *)vals))
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return;
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*vals |= 0x02;
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if (0 != sia81xx_regmap_write(regmap, SIA8159_REG_ALGO_CFG2, 1, (char *)vals))
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return;
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sia81xx_regmap_write(regmap,
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SIA8159_REG_TRIMMING_BEGIN, reg_num, defaults);
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}
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}
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const struct sia81xx_opt_if sia8159_opt_if = {
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.check_chip_id = sia8159_check_chip_id,
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.set_xfilter = NULL,
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.chip_on = sia8159_chip_on,
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.chip_off = sia8159_chip_off,
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.get_chip_en = NULL,
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.set_pvdd_limit = NULL,
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.check_trimming = sia8159_check_trimming,
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};
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