threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*
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* Intel Atom platform clocks for BayTrail and CherryTrail SoC.
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Irina Tirdea <irina.tirdea@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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#define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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/**
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* struct pmc_clk - PMC platform clock configuration
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*
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* @name: identified, typically pmc_plt_clk_<x>, x=[0..5]
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* @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported
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* @parent_name: one of 'xtal' or 'osc'
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*/
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struct pmc_clk {
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const char *name;
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unsigned long freq;
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const char *parent_name;
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};
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/**
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* struct pmc_clk_data - common PMC clock configuration
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*
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* @base: PMC clock register base offset
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* @clks: pointer to set of registered clocks, typically 0..5
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* @critical: flag to indicate if firmware enabled pmc_plt_clks
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* should be marked as critial or not
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*/
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struct pmc_clk_data {
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void __iomem *base;
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const struct pmc_clk *clks;
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bool critical;
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};
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#endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */
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