threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/*
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* DaVinci GPIO Platform Related Defines
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_GPIO_PLATFORM_H
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#define __DAVINCI_GPIO_PLATFORM_H
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <asm-generic/gpio.h>
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#define MAX_REGS_BANKS 5
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struct davinci_gpio_platform_data {
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u32 ngpio;
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u32 gpio_unbanked;
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};
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struct davinci_gpio_irq_data {
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void __iomem *regs;
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struct davinci_gpio_controller *chip;
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int bank_num;
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};
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struct davinci_gpio_controller {
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struct gpio_chip chip;
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struct irq_domain *irq_domain;
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/* Serialize access to GPIO registers */
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spinlock_t lock;
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void __iomem *regs[MAX_REGS_BANKS];
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int gpio_unbanked;
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unsigned int base_irq;
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unsigned int base;
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};
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/*
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* basic gpio routines
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*/
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#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
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/* Convert GPIO signal to GPIO pin number */
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#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
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static inline u32 __gpio_mask(unsigned gpio)
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{
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return 1 << (gpio % 32);
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}
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#endif
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