threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
|
|
* TI EDMA definitions
|
|
*
|
|
* Copyright (C) 2006-2013 Texas Instruments.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/*
|
|
* This EDMA3 programming framework exposes two basic kinds of resource:
|
|
*
|
|
* Channel Triggers transfers, usually from a hardware event but
|
|
* also manually or by "chaining" from DMA completions.
|
|
* Each channel is coupled to a Parameter RAM (PaRAM) slot.
|
|
*
|
|
* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
|
|
* "set"), source and destination addresses, a link to a
|
|
* next PaRAM slot (if any), options for the transfer, and
|
|
* instructions for updating those addresses. There are
|
|
* more than twice as many slots as event channels.
|
|
*
|
|
* Each PaRAM set describes a sequence of transfers, either for one large
|
|
* buffer or for several discontiguous smaller buffers. An EDMA transfer
|
|
* is driven only from a channel, which performs the transfers specified
|
|
* in its PaRAM slot until there are no more transfers. When that last
|
|
* transfer completes, the "link" field may be used to reload the channel's
|
|
* PaRAM slot with a new transfer descriptor.
|
|
*
|
|
* The EDMA Channel Controller (CC) maps requests from channels into physical
|
|
* Transfer Controller (TC) requests when the channel triggers (by hardware
|
|
* or software events, or by chaining). The two physical DMA channels provided
|
|
* by the TCs are thus shared by many logical channels.
|
|
*
|
|
* DaVinci hardware also has a "QDMA" mechanism which is not currently
|
|
* supported through this interface. (DSP firmware uses it though.)
|
|
*/
|
|
|
|
#ifndef EDMA_H_
|
|
#define EDMA_H_
|
|
|
|
enum dma_event_q {
|
|
EVENTQ_0 = 0,
|
|
EVENTQ_1 = 1,
|
|
EVENTQ_2 = 2,
|
|
EVENTQ_3 = 3,
|
|
EVENTQ_DEFAULT = -1
|
|
};
|
|
|
|
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
|
|
#define EDMA_CTLR(i) ((i) >> 16)
|
|
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
|
|
|
|
#define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
|
|
|
|
struct edma_rsv_info {
|
|
|
|
const s16 (*rsv_chans)[2];
|
|
const s16 (*rsv_slots)[2];
|
|
};
|
|
|
|
struct dma_slave_map;
|
|
|
|
/* platform_data for EDMA driver */
|
|
struct edma_soc_info {
|
|
/*
|
|
* Default queue is expected to be a low-priority queue.
|
|
* This way, long transfers on the default queue started
|
|
* by the codec engine will not cause audio defects.
|
|
*/
|
|
enum dma_event_q default_queue;
|
|
|
|
/* Resource reservation for other cores */
|
|
struct edma_rsv_info *rsv;
|
|
|
|
/* List of channels allocated for memcpy, terminated with -1 */
|
|
s32 *memcpy_channels;
|
|
|
|
s8 (*queue_priority_mapping)[2];
|
|
const s16 (*xbar_chans)[2];
|
|
|
|
const struct dma_slave_map *slave_map;
|
|
int slavecnt;
|
|
};
|
|
|
|
#endif
|