threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
64 lines
2.4 KiB
C
64 lines
2.4 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8173
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/* INFRACFG resets */
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#define MT8173_INFRA_EMI_REG_RST 0
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#define MT8173_INFRA_DRAMC0_A0_RST 1
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#define MT8173_INFRA_APCIRQ_EINT_RST 3
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#define MT8173_INFRA_APXGPT_RST 4
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#define MT8173_INFRA_SCPSYS_RST 5
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#define MT8173_INFRA_KP_RST 6
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#define MT8173_INFRA_PMIC_WRAP_RST 7
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#define MT8173_INFRA_MPIP_RST 8
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#define MT8173_INFRA_CEC_RST 9
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#define MT8173_INFRA_EMI_RST 32
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#define MT8173_INFRA_DRAMC0_RST 34
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#define MT8173_INFRA_APMIXEDSYS_RST 35
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#define MT8173_INFRA_MIPI_DSI_RST 36
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#define MT8173_INFRA_TRNG_RST 37
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#define MT8173_INFRA_SYSIRQ_RST 38
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#define MT8173_INFRA_MIPI_CSI_RST 39
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#define MT8173_INFRA_GCE_FAXI_RST 40
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#define MT8173_INFRA_MMIOMMURST 47
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/* PERICFG resets */
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#define MT8173_PERI_UART0_SW_RST 0
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#define MT8173_PERI_UART1_SW_RST 1
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#define MT8173_PERI_UART2_SW_RST 2
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#define MT8173_PERI_UART3_SW_RST 3
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#define MT8173_PERI_IRRX_SW_RST 4
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#define MT8173_PERI_PWM_SW_RST 8
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#define MT8173_PERI_AUXADC_SW_RST 10
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#define MT8173_PERI_DMA_SW_RST 11
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#define MT8173_PERI_I2C6_SW_RST 13
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#define MT8173_PERI_NFI_SW_RST 14
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#define MT8173_PERI_THERM_SW_RST 16
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#define MT8173_PERI_MSDC2_SW_RST 17
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#define MT8173_PERI_MSDC3_SW_RST 18
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#define MT8173_PERI_MSDC0_SW_RST 19
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#define MT8173_PERI_MSDC1_SW_RST 20
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#define MT8173_PERI_I2C0_SW_RST 22
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#define MT8173_PERI_I2C1_SW_RST 23
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#define MT8173_PERI_I2C2_SW_RST 24
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#define MT8173_PERI_I2C3_SW_RST 25
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#define MT8173_PERI_I2C4_SW_RST 26
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#define MT8173_PERI_HDMI_SW_RST 29
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#define MT8173_PERI_SPI0_SW_RST 33
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */
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