threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for the PRCMU bindings.
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*
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*/
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#ifndef _DT_BINDINGS_MFD_PRCMU_H
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#define _DT_BINDINGS_MFD_PRCMU_H
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/*
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* Clock identifiers.
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*/
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#define ARMCLK 0
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#define PRCMU_ACLK 1
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#define PRCMU_SVAMMCSPCLK 2
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#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
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#define PRCMU_SIACLK 3
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#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
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#define PRCMU_SGACLK 4
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#define PRCMU_UARTCLK 5
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#define PRCMU_MSP02CLK 6
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#define PRCMU_MSP1CLK 7
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#define PRCMU_I2CCLK 8
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#define PRCMU_SDMMCCLK 9
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#define PRCMU_SLIMCLK 10
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#define PRCMU_CAMCLK 10 /* DBx540 only. */
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#define PRCMU_PER1CLK 11
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#define PRCMU_PER2CLK 12
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#define PRCMU_PER3CLK 13
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#define PRCMU_PER5CLK 14
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#define PRCMU_PER6CLK 15
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#define PRCMU_PER7CLK 16
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#define PRCMU_LCDCLK 17
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#define PRCMU_BMLCLK 18
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#define PRCMU_HSITXCLK 19
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#define PRCMU_HSIRXCLK 20
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#define PRCMU_HDMICLK 21
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#define PRCMU_APEATCLK 22
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#define PRCMU_APETRACECLK 23
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#define PRCMU_MCDECLK 24
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#define PRCMU_IPI2CCLK 25
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#define PRCMU_DSIALTCLK 26
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#define PRCMU_DMACLK 27
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#define PRCMU_B2R2CLK 28
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#define PRCMU_TVCLK 29
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#define SPARE_UNIPROCLK 30
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#define PRCMU_SSPCLK 31
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#define PRCMU_RNGCLK 32
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#define PRCMU_UICCCLK 33
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#define PRCMU_G1CLK 34 /* DBx540 only. */
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#define PRCMU_HVACLK 35 /* DBx540 only. */
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#define PRCMU_SPARE1CLK 36
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#define PRCMU_SPARE2CLK 37
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#define PRCMU_NUM_REG_CLOCKS 38
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#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
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#define PRCMU_SYSCLK 39
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#define PRCMU_CDCLK 40
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#define PRCMU_TIMCLK 41
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#define PRCMU_PLLSOC0 42
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#define PRCMU_PLLSOC1 43
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#define PRCMU_ARMSS 44
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#define PRCMU_PLLDDR 45
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/* DSI Clocks */
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#define PRCMU_PLLDSI 46
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#define PRCMU_DSI0CLK 47
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#define PRCMU_DSI1CLK 48
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#define PRCMU_DSI0ESCCLK 49
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#define PRCMU_DSI1ESCCLK 50
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#define PRCMU_DSI2ESCCLK 51
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/* LCD DSI PLL - Ux540 only */
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#define PRCMU_PLLDSI_LCD 52
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#define PRCMU_DSI0CLK_LCD 53
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#define PRCMU_DSI1CLK_LCD 54
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#define PRCMU_DSI0ESCCLK_LCD 55
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#define PRCMU_DSI1ESCCLK_LCD 56
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#define PRCMU_DSI2ESCCLK_LCD 57
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#define PRCMU_NUM_CLKS 58
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#endif
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