threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
60 lines
1.2 KiB
C
60 lines
1.2 KiB
C
/*
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* stm32fx-clock.h
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*
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* Copyright (C) 2016 STMicroelectronics
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* Author: Gabriel Fernandez for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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/*
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* List of clocks wich are not derived from system clock (SYSCLOCK)
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*
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* The index of these clocks is the secondary index of DT bindings
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* (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
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*
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* e.g:
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<assigned-clocks = <&rcc 1 CLK_LSE>;
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*/
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#ifndef _DT_BINDINGS_CLK_STMFX_H
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#define _DT_BINDINGS_CLK_STMFX_H
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#define SYSTICK 0
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#define FCLK 1
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#define CLK_LSI 2
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#define CLK_LSE 3
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#define CLK_HSE_RTC 4
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#define CLK_RTC 5
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#define PLL_VCO_I2S 6
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#define PLL_VCO_SAI 7
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#define CLK_LCD 8
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#define CLK_I2S 9
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#define CLK_SAI1 10
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#define CLK_SAI2 11
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#define CLK_I2SQ_PDIV 12
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#define CLK_SAIQ_PDIV 13
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#define END_PRIMARY_CLK 14
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#define CLK_HSI 14
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#define CLK_SYSCLK 15
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#define CLK_HDMI_CEC 16
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#define CLK_SPDIF 17
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#define CLK_USART1 18
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#define CLK_USART2 19
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#define CLK_USART3 20
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#define CLK_UART4 21
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#define CLK_UART5 22
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#define CLK_USART6 23
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#define CLK_UART7 24
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#define CLK_UART8 25
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#define CLK_I2C1 26
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#define CLK_I2C2 27
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#define CLK_I2C3 28
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#define CLK_I2C4 29
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#define CLK_LPTIMER 30
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#define END_PRIMARY_CLK_F7 31
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#endif
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