threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/*
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* ARTPEC-6 clock controller indexes
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*
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* Copyright 2016 Axis Comunications AB.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
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#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
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#define ARTPEC6_CLK_CPU 0
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#define ARTPEC6_CLK_CPU_PERIPH 1
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#define ARTPEC6_CLK_NAND_CLKA 2
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#define ARTPEC6_CLK_NAND_CLKB 3
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#define ARTPEC6_CLK_ETH_ACLK 4
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#define ARTPEC6_CLK_DMA_ACLK 5
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#define ARTPEC6_CLK_PTP_REF 6
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#define ARTPEC6_CLK_SD_PCLK 7
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#define ARTPEC6_CLK_SD_IMCLK 8
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#define ARTPEC6_CLK_I2S_HST 9
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#define ARTPEC6_CLK_I2S0_CLK 10
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#define ARTPEC6_CLK_I2S1_CLK 11
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#define ARTPEC6_CLK_UART_PCLK 12
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#define ARTPEC6_CLK_UART_REFCLK 13
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#define ARTPEC6_CLK_I2C 14
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#define ARTPEC6_CLK_SPI_PCLK 15
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#define ARTPEC6_CLK_SPI_SSPCLK 16
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#define ARTPEC6_CLK_SYS_TIMER 17
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#define ARTPEC6_CLK_FRACDIV_IN 18
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#define ARTPEC6_CLK_DBG_PCLK 19
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/* This must be the highest clock index plus one. */
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#define ARTPEC6_CLK_NUMCLOCKS 20
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#endif
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