Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <Owen.Chen@mediatek.com>
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*/
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#include <linux/ktime.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/soc/mediatek/scpsys-ext.h>
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#define MTK_POLL_DELAY_US 10
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#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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static int set_way_en(struct regmap *map, struct regmap *ack, u32 mask,
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u32 ack_mask, u32 reg_set, u32 reg_sta,
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u32 reg_en)
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{
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u32 val;
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if (reg_set)
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regmap_write(map, reg_set, mask);
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else
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regmap_update_bits(map, reg_en, mask, mask);
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return regmap_read_poll_timeout(ack, reg_sta,
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val, (val & ack_mask) == ack_mask,
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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}
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static int clear_way_en(struct regmap *map, struct regmap *ack, u32 mask,
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u32 ack_mask, u32 reg_clr, u32 reg_sta,
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u32 reg_en)
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{
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u32 val;
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if (reg_clr)
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regmap_write(map, reg_clr, mask);
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else
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regmap_update_bits(map, reg_en, mask, 0);
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return regmap_read_poll_timeout(ack, reg_sta,
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val, (val & ack_mask) == ack_mask,
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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}
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static int set_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
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u32 reg_set, u32 reg_sta, u32 reg_en)
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{
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u32 val;
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if (reg_set)
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regmap_write(map, reg_set, mask);
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else
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regmap_update_bits(map, reg_en, mask, mask);
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return regmap_read_poll_timeout(map, reg_sta,
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val, (val & ack_mask) == ack_mask,
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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}
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static int clear_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
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u32 reg_clr, u32 reg_sta, u32 reg_en)
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{
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u32 val;
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if (reg_clr)
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regmap_write(map, reg_clr, mask);
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else
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regmap_update_bits(map, reg_en, mask, 0);
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return regmap_read_poll_timeout(map, reg_sta,
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val, !(val & ack_mask),
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
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}
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int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
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struct regmap *infracfg, struct regmap *smi_common,
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struct regmap *infracfg_nao)
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{
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int i;
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for (i = 0; i < MAX_STEPS && bp_table[i].mask; i++) {
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int ret;
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switch (bp_table[i].type) {
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case IFR_TYPE:
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ret = set_bus_protection(infracfg, bp_table[i].mask,
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bp_table[i].mask, bp_table[i].set_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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case SMI_TYPE:
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ret = set_bus_protection(smi_common, bp_table[i].mask,
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bp_table[i].mask, bp_table[i].set_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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case IFR_WAYEN_TYPE:
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ret = clear_way_en(infracfg, infracfg_nao,
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bp_table[i].mask,
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bp_table[i].clr_ack_mask,
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bp_table[i].clr_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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default:
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return -EINVAL;
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}
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if (ret)
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return ret;
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}
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return 0;
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}
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int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
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struct regmap *infracfg, struct regmap *smi_common,
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struct regmap *infracfg_nao)
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{
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int i;
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for (i = MAX_STEPS - 1; i >= 0; i--) {
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int ret;
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switch (bp_table[i].type) {
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case IFR_TYPE:
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ret = clear_bus_protection(infracfg, bp_table[i].mask,
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bp_table[i].clr_ack_mask,
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bp_table[i].clr_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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case SMI_TYPE:
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ret = clear_bus_protection(smi_common,
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bp_table[i].mask,
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bp_table[i].clr_ack_mask,
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bp_table[i].clr_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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case IFR_WAYEN_TYPE:
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ret = set_way_en(infracfg, infracfg_nao,
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bp_table[i].mask,
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bp_table[i].set_ack_mask,
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bp_table[i].set_ofs,
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bp_table[i].sta_ofs,
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bp_table[i].en_ofs);
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break;
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default:
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return -EINVAL;
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}
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if (ret)
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return ret;
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}
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return 0;
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}
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