threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
750 lines
19 KiB
C
750 lines
19 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "ufs.h"
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#include "ufshcd.h"
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#include "ufs_quirks.h"
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#include "unipro.h"
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#include "ufs-mtk.h"
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#include "ufs-mtk-platform.h"
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#include "mtk_idle.h"
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#include "mtk_spm_resource_req.h"
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#include "mtk_secure_api.h"
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#ifdef MTK_UFS_HQA
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#include <mtk_reboot.h>
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#endif
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#ifdef UPMU_READY
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#include <mt-plat/upmu_common.h>
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#endif
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#ifdef CLKBUF_READY
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#include "mtk_clkbuf_ctl.h"
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#endif
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static void __iomem *ufs_mtk_mmio_base_gpio;
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static void __iomem *ufs_mtk_mmio_base_infracfg_ao;
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static void __iomem *ufs_mtk_mmio_base_ufs_mphy;
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static struct regulator *reg_va09;
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/**
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* ufs_mtk_pltfrm_pwr_change_final_gear - change pwr mode fianl gear value.
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*/
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void ufs_mtk_pltfrm_pwr_change_final_gear(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *final)
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{
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/* Change final gear if necessary */
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}
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#ifdef MTK_UFS_HQA
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/* UFS write is performance 200MB/s, 4KB will take around 20us */
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/* Set delay before reset to 100us to cover 4KB & >4KB write */
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#define UFS_SPOH_USDELAY_BEFORE_RESET (100)
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void random_delay(struct ufs_hba *hba)
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{
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u32 time = (sched_clock()%UFS_SPOH_USDELAY_BEFORE_RESET);
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udelay(time);
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}
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void wdt_pmic_full_reset(struct ufs_hba *hba)
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{
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/*
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* Cmd issue to PMIC on MT6771 will take around 20us ~ 30us, in order
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* to speed up VEMC disable time, we disable VEMC first coz PMIC cold
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* reset may take longer to disable VEMC in it's reset flow. Can not
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* use regulator_disable() here because it can not use in preemption
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* disabled context. Use pmic raw API without nlock instead.
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*/
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pmic_set_register_value_nolock(PMIC_RG_LDO_VEMC_EN, 0);
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/* Need reset external LDO for VUFS18, UFS needs VEMC&VUFS18 reset at
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* the same time
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*/
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pmic_set_register_value_nolock(PMIC_RG_STRUP_EXT_PMIC_SEL, 0x1);
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/* VA09 off, may not require */
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/* pmic_set_register_value_nolock(PMIC_RG_STRUP_EXT_PMIC_EN, 0x1); */
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/* pmic_set_register_value_nolock(PMIC_RG_STRUP_EXT_PMIC_SEL, 0x2); */
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/* PMIC cold reset */
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pmic_set_register_value_nolock(PMIC_RG_CRST, 1);
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}
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#endif
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#define PMIC_REG_MASK (0xFFFF)
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#define PMIC_REG_SHIFT (0)
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void ufs_mtk_pltfrm_gpio_trigger_and_debugInfo_dump(struct ufs_hba *hba)
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{
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#ifdef UPMU_READY
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int vcc_enabled, vcc_value, vccq2_enabled, va09_enabled;
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vcc_enabled = pmic_get_register_value(PMIC_RG_LDO_VEMC_EN);
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vcc_value = pmic_get_register_value(PMIC_RG_VEMC_VOSEL);
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vccq2_enabled = pmic_get_register_value(PMIC_DA_EXT_PMIC_EN1);
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va09_enabled = pmic_get_register_value(PMIC_DA_EXT_PMIC_EN1);
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/* dump vcc, vccq2 and va09 info */
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dev_info(hba->dev,
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"vcc_enabled:%d, vcc_value:%d, vccq2_enabled:%d, va09:%d!!!\n",
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vcc_enabled, vcc_value, vccq2_enabled, va09_enabled);
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/* dump clock buffer */
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clk_buf_dump_clkbuf_log();
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#endif
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}
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#ifdef CONFIG_MTK_UFS_DEGUG_GPIO_TRIGGER
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#include <mt-plat/sync_write.h>
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struct device_node *msdc_gpio_node;
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void __iomem *msdc_gpio_base;
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static struct regulator *vmc;
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#define MSDC1_GPIO_MODE17 (msdc_gpio_base + 0x410)
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#define MSDC1_GPIO_DIR4 (msdc_gpio_base + 0x40)
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#define MSDC1_GPIO_DOUT4 (msdc_gpio_base + 0x140)
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#define MSDC1_GPIO_DOUT (MSDC1_GPIO_DOUT4)
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#define MSDC1_GPIO_DOUT_DIR_FIELD (0x00000F00)
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#define MSDC1_GPIO_DOUT_DIR_VAL_SET (0x0000000F)
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#define MSDC1_GPIO_DOUT_DIR_VAL_CLR (0x00000000)
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#define MSDC_READ32(reg) __raw_readl(reg)
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#define MSDC_WRITE32(reg, val) mt_reg_sync_writel(val, reg)
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static inline unsigned int uffs(unsigned int x)
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{
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unsigned int r = 1;
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if (!x)
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return 0;
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if (!(x & 0xffff)) {
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x >>= 16;
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r += 16;
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}
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if (!(x & 0xff)) {
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x >>= 8;
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r += 8;
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}
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if (!(x & 0xf)) {
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x >>= 4;
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r += 4;
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}
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if (!(x & 3)) {
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x >>= 2;
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r += 2;
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}
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if (!(x & 1)) {
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x >>= 1;
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r += 1;
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}
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return r;
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}
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#define MSDC_SET_FIELD(reg, field, val) \
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do { \
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unsigned int tv = MSDC_READ32(reg); \
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tv &= ~(field); \
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tv |= ((val) << (uffs((unsigned int)field) - 1)); \
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MSDC_WRITE32(reg, tv); \
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} while (0)
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void ufs_mtk_pltfrm_gpio_trigger_init(struct ufs_hba *hba)
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{
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/* Need porting for UFS Debug*/
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/* Set gpio mode */
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/* Set gpio output */
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/* Set gpio default low */
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dev_info(hba->dev, "%s: trigger_gpio_init!!!\n",
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__func__);
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if (msdc_gpio_node == NULL) {
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msdc_gpio_node = of_find_compatible_node(NULL, NULL,
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"mediatek,GPIO");
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msdc_gpio_base = of_iomap(msdc_gpio_node, 0);
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pr_notice("of_iomap for gpio base @ 0x%p\n", msdc_gpio_base);
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};
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/*
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* Power on
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* Be sure add dts in ufs node
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* vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
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*/
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vmc = regulator_get(hba->dev, "vqmmc");
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if (!IS_ERR(vmc)) {
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regulator_set_voltage(vmc, VOL_3000 * 1000, VOL_3000 * 1000);
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regulator_enable(vmc);
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}
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/*
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* Set gpio to gpio mode. (dat0/dat1/dat2/dat3 in GPIO)
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* Be sure remove msdc_set_pin_mode in msdc_cust.c set mode
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* back to msdc.
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*/
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MSDC_SET_FIELD(MSDC1_GPIO_MODE17, 0x0000FFFF, 0x0);
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/*
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* Set gpio dir output. (dat0/dat1/dat2/dat3 in GPIO)
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*/
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MSDC_SET_FIELD(MSDC1_GPIO_DIR4,
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MSDC1_GPIO_DOUT_DIR_FIELD,
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MSDC1_GPIO_DOUT_DIR_VAL_SET);
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/*
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* Set gpio output 0. (dat0/dat1/dat2/dat3 in GPIO)
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*/
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MSDC_SET_FIELD(MSDC1_GPIO_DOUT,
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MSDC1_GPIO_DOUT_DIR_FIELD,
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MSDC1_GPIO_DOUT_DIR_VAL_CLR);
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}
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void ufs_mtk_pltfrm_gpio_trigger(int value)
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{
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if (-EPROBE_DEFER == PTR_ERR(vmc)) {
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vmc = regulator_get(ufs_mtk_hba->dev, "vqmmc");
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if (!IS_ERR(vmc)) {
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regulator_set_voltage(vmc,
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VOL_3000 * 1000, VOL_3000 * 1000);
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regulator_enable(vmc);
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}
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}
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if (value == 1) {
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MSDC_SET_FIELD(MSDC1_GPIO_DOUT,
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MSDC1_GPIO_DOUT_DIR_FIELD,
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MSDC1_GPIO_DOUT_DIR_VAL_SET);
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} else {
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MSDC_SET_FIELD(MSDC1_GPIO_DOUT,
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MSDC1_GPIO_DOUT_DIR_FIELD,
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MSDC1_GPIO_DOUT_DIR_VAL_CLR);
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}
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pr_notice("error trigger, %d\n", value);
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pr_info("%s vmc=%d uv\n", __func__, regulator_get_voltage(vmc));
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pr_info("%s mode=0x%x, dir=0x%x, out=0x%x\n", __func__,
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MSDC_READ32(MSDC1_GPIO_MODE17),
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MSDC_READ32(MSDC1_GPIO_DIR4),
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MSDC_READ32(MSDC1_GPIO_DOUT));
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}
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#endif
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int ufs_mtk_pltfrm_xo_ufs_req(struct ufs_hba *hba, bool on)
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{
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u32 value;
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if (!hba->card) {
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/*
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* In case card is not init, just ignore it.
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* Because clock is default on.
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* After card init done the clk control
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* will be normal.
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*/
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dev_info(hba->dev, "%s: card not init skip\n",
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__func__);
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return 0;
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}
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/*
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* Delay before disable ref-clk: H8 -> delay A -> disable ref-clk
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* delayA
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* Hynix 30us
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* Samsung 1us
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* Toshiba 100us
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*/
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if (!on) {
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switch (hba->card->wmanufacturerid) {
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case UFS_VENDOR_TOSHIBA:
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udelay(100);
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break;
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case UFS_VENDOR_SKHYNIX:
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udelay(30);
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break;
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case UFS_VENDOR_SAMSUNG:
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udelay(1);
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break;
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default:
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udelay(30);
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break;
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}
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}
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if (on) {
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clk_buf_ctrl(CLK_BUF_UFS, true);
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} else {
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clk_buf_ctrl(CLK_BUF_UFS, false);
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spm_resource_req(SPM_RESOURCE_USER_UFS, SPM_RESOURCE_RELEASE);
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}
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/* Delay after enable ref-clk: enable ref-clk -> delay B -> leave H8
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* delayB
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* Hynix 30us
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* Samsung max(1us,32us)
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* Toshiba 32us
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*/
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if (on) {
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switch (hba->card->wmanufacturerid) {
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case UFS_VENDOR_TOSHIBA:
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udelay(32);
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break;
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case UFS_VENDOR_SKHYNIX:
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udelay(30);
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break;
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case UFS_VENDOR_SAMSUNG:
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udelay(32);
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break;
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default:
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udelay(30);
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break;
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}
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}
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return 0;
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}
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int ufs_mtk_pltfrm_ufs_device_reset(struct ufs_hba *hba)
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{
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mt_secure_call(MTK_SIP_KERNEL_UFS_CTL, 2, 0, 0, 0);
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/*
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* The reset signal is active low.
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* The UFS device shall detect more than or equal to 1us of positive
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* or negative RST_n pulse width.
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* To be on safe side, keep the reset low for at least 10us.
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*/
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usleep_range(10, 15);
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mt_secure_call(MTK_SIP_KERNEL_UFS_CTL, 2, 1, 0, 0);
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/* some device may need time to respond to rst_n */
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usleep_range(10000, 15000);
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dev_info(hba->dev, "%s: UFS device reset done\n", __func__);
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return 0;
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}
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/*
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* In early-porting stage, because of no bootrom,
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* something finished by bootrom shall be finished here instead.
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* Returns:
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* 0: Successful.
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* Non-zero: Failed.
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*/
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int ufs_mtk_pltfrm_bootrom_deputy(struct ufs_hba *hba)
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{
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#ifdef CONFIG_FPGA_EARLY_PORTING
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mt_secure_call(MTK_SIP_KERNEL_UFS_CTL, 2, 1, 0, 0);
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#endif
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#ifdef CONFIG_MTK_UFS_DEGUG_GPIO_TRIGGER
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ufs_mtk_pltfrm_gpio_trigger_init(hba);
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#endif
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return 0;
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}
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int ufs_mtk_pltfrm_ref_clk_ctrl(struct ufs_hba *hba, bool on)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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int ret = 0;
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u32 val = 0;
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if (on) {
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/* Host need turn on clock by itself */
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ret = ufs_mtk_pltfrm_xo_ufs_req(hba, true);
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if (ret)
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goto out;
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} else {
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val = VENDOR_POWERSTATE_HIBERNATE;
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ufs_mtk_wait_link_state(hba, &val,
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hba->clk_gating.delay_ms);
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if (val == VENDOR_POWERSTATE_HIBERNATE) {
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/* Host need turn off clock by itself */
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ret = ufs_mtk_pltfrm_xo_ufs_req(hba, false);
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if (ret)
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goto out;
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} else if (val == VENDOR_POWERSTATE_DISABLED) {
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/* hba stop after shoutdown, do nothing */
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} else {
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dev_info(hba->dev, "%s: power state (%d) clk not off\n",
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__func__, val);
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dev_info(hba->dev, "%s: ah8_en(%d), ah_reg = 0x%x\n",
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__func__,
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ufs_mtk_auto_hibern8_enabled,
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ufshcd_readl(hba,
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REG_AUTO_HIBERNATE_IDLE_TIMER));
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}
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}
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out:
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return ret;
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}
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/**
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* ufs_mtk_deepidle_hibern8_check - callback function for Deepidle & SODI.
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* Release all resources: DRAM/26M clk/Main PLL and dsiable 26M ref clk if
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* in H8.
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*
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* @return: 0 for success, negative/postive error code otherwise
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*/
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int ufs_mtk_pltfrm_deepidle_check_h8(void)
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{
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/* No Need for MT6785 */
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return 0;
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}
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/**
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* ufs_mtk_deepidle_leave - callback function for leaving Deepidle & SODI.
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*/
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void ufs_mtk_pltfrm_deepidle_leave(void)
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{
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/* No Need for MT6785 */
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}
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/**
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* ufs_mtk_pltfrm_deepidle_lock - Deepidle & SODI lock.
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* @hba: per-adapter instance
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* @lock: lock or unlock deepidle & SODI entrance.
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*/
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void ufs_mtk_pltfrm_deepidle_lock(struct ufs_hba *hba, bool lock)
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{
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/* No Need for MT6785 */
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}
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int ufs_mtk_pltfrm_host_sw_rst(struct ufs_hba *hba, u32 target)
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{
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u32 reg;
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if (!ufs_mtk_mmio_base_infracfg_ao) {
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dev_info(hba->dev,
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"ufs_mtk_host_sw_rst: failed, null ufs_mtk_mmio_base_infracfg_ao.\n");
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return 1;
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}
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dev_dbg(hba->dev, "ufs_mtk_host_sw_rst: 0x%x\n", target);
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if (target & SW_RST_TARGET_UFSHCI) {
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/* reset HCI */
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reg = readl(ufs_mtk_mmio_base_infracfg_ao +
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REG_UFSHCI_SW_RST_SET);
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reg = reg | (1 << REG_UFSHCI_SW_RST_SET_BIT);
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writel(reg,
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ufs_mtk_mmio_base_infracfg_ao + REG_UFSHCI_SW_RST_SET);
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}
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if (target & SW_RST_TARGET_UFSCPT) {
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/* reset AES */
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reg = readl(ufs_mtk_mmio_base_infracfg_ao +
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REG_UFSCPT_SW_RST_SET);
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reg = reg | (1 << REG_UFSCPT_SW_RST_SET_BIT);
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writel(reg,
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ufs_mtk_mmio_base_infracfg_ao + REG_UFSCPT_SW_RST_SET);
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}
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if (target & SW_RST_TARGET_UNIPRO) {
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/* reset UniPro */
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reg = readl(ufs_mtk_mmio_base_infracfg_ao +
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REG_UNIPRO_SW_RST_SET);
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reg = reg | (1 << REG_UNIPRO_SW_RST_SET_BIT);
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writel(reg,
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ufs_mtk_mmio_base_infracfg_ao + REG_UNIPRO_SW_RST_SET);
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}
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if (target & SW_RST_TARGET_MPHY) {
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/* reset Mphy */
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reg = readl(ufs_mtk_mmio_base_infracfg_ao +
|
|
REG_UFSPHY_SW_RST_SET);
|
|
reg = reg | (1 << REG_UFSPHY_SW_RST_SET_BIT);
|
|
writel(reg,
|
|
ufs_mtk_mmio_base_infracfg_ao + REG_UFSPHY_SW_RST_SET);
|
|
}
|
|
|
|
udelay(100);
|
|
|
|
if (target & SW_RST_TARGET_UFSHCI) {
|
|
/* clear HCI reset */
|
|
reg = readl(ufs_mtk_mmio_base_infracfg_ao +
|
|
REG_UFSHCI_SW_RST_CLR);
|
|
reg = reg | (1 << REG_UFSHCI_SW_RST_CLR_BIT);
|
|
writel(reg,
|
|
ufs_mtk_mmio_base_infracfg_ao + REG_UFSHCI_SW_RST_CLR);
|
|
}
|
|
|
|
if (target & SW_RST_TARGET_UFSCPT) {
|
|
/* clear AES reset */
|
|
reg = readl(ufs_mtk_mmio_base_infracfg_ao +
|
|
REG_UFSCPT_SW_RST_CLR);
|
|
reg = reg | (1 << REG_UFSCPT_SW_RST_CLR_BIT);
|
|
writel(reg,
|
|
ufs_mtk_mmio_base_infracfg_ao + REG_UFSCPT_SW_RST_CLR);
|
|
}
|
|
|
|
if (target & SW_RST_TARGET_UNIPRO) {
|
|
/* clear UniPro reset */
|
|
reg = readl(ufs_mtk_mmio_base_infracfg_ao +
|
|
REG_UNIPRO_SW_RST_CLR);
|
|
reg = reg | (1 << REG_UNIPRO_SW_RST_CLR_BIT);
|
|
writel(reg,
|
|
ufs_mtk_mmio_base_infracfg_ao + REG_UNIPRO_SW_RST_CLR);
|
|
}
|
|
|
|
if (target & SW_RST_TARGET_MPHY) {
|
|
/* clear Mphy reset */
|
|
reg = readl(ufs_mtk_mmio_base_infracfg_ao +
|
|
REG_UFSPHY_SW_RST_CLR);
|
|
reg = reg | (1 << REG_UFSPHY_SW_RST_CLR_BIT);
|
|
writel(reg,
|
|
ufs_mtk_mmio_base_infracfg_ao + REG_UFSPHY_SW_RST_CLR);
|
|
}
|
|
|
|
udelay(100);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ufs_mtk_pltfrm_init(void)
|
|
{
|
|
ufs_mtk_hba->caps |= UFSHCD_CAP_CLK_GATING;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ufs_mtk_pltfrm_parse_dt(struct ufs_hba *hba)
|
|
{
|
|
struct device_node *node_gpio;
|
|
struct device_node *node_ufs_mphy;
|
|
struct device_node *node_infracfg_ao;
|
|
int err = 0;
|
|
|
|
/* get ufs_mtk_gpio */
|
|
node_gpio = of_find_compatible_node(NULL, NULL, "mediatek,gpio");
|
|
|
|
if (node_gpio) {
|
|
ufs_mtk_mmio_base_gpio = of_iomap(node_gpio, 0);
|
|
|
|
if (IS_ERR(*(void **)&ufs_mtk_mmio_base_gpio)) {
|
|
err = PTR_ERR(*(void **)&ufs_mtk_mmio_base_gpio);
|
|
dev_err(hba->dev, "error: ufs_mtk_mmio_base_gpio init fail\n");
|
|
ufs_mtk_mmio_base_gpio = NULL;
|
|
}
|
|
} else
|
|
dev_err(hba->dev, "error: node_gpio init fail\n");
|
|
|
|
/* get ufs_mtk_mmio_base_ufs_mphy */
|
|
|
|
node_ufs_mphy =
|
|
of_find_compatible_node(NULL, NULL, "mediatek,ufs_mphy");
|
|
|
|
if (node_ufs_mphy) {
|
|
ufs_mtk_mmio_base_ufs_mphy = of_iomap(node_ufs_mphy, 0);
|
|
|
|
if (IS_ERR(*(void **)&ufs_mtk_mmio_base_ufs_mphy)) {
|
|
err = PTR_ERR(*(void **)&ufs_mtk_mmio_base_ufs_mphy);
|
|
dev_err(hba->dev, "error: ufs_mtk_mmio_base_ufs_mphy init fail\n");
|
|
ufs_mtk_mmio_base_ufs_mphy = NULL;
|
|
}
|
|
} else
|
|
dev_err(hba->dev, "error: ufs_mtk_mmio_base_ufs_mphy init fail\n");
|
|
|
|
|
|
/* get ufs_mtk_mmio_base_infracfg_ao */
|
|
node_infracfg_ao =
|
|
of_find_compatible_node(NULL, NULL, "mediatek,infracfg_ao");
|
|
if (node_infracfg_ao) {
|
|
ufs_mtk_mmio_base_infracfg_ao = of_iomap(node_infracfg_ao, 0);
|
|
|
|
if (IS_ERR(*(void **)&ufs_mtk_mmio_base_infracfg_ao)) {
|
|
err = PTR_ERR(*(void **)&ufs_mtk_mmio_base_infracfg_ao);
|
|
dev_err(hba->dev, "error: ufs_mtk_mmio_base_infracfg_ao init fail\n");
|
|
ufs_mtk_mmio_base_infracfg_ao = NULL;
|
|
}
|
|
} else
|
|
dev_err(hba->dev, "error: ufs_mtk_mmio_base_infracfg_ao init fail\n");
|
|
|
|
/* get va09 regulator and enable it */
|
|
reg_va09 = regulator_get(hba->dev, "va09");
|
|
if (!reg_va09) {
|
|
dev_info(hba->dev, "%s: get va09 fail!!!\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
err = regulator_enable(reg_va09);
|
|
if (err < 0) {
|
|
dev_info(hba->dev, "%s: enalbe va09 fail, err = %d\n",
|
|
__func__, err);
|
|
return err;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int ufs_mtk_pltfrm_resume(struct ufs_hba *hba)
|
|
{
|
|
int ret = 0;
|
|
u32 reg;
|
|
|
|
#ifdef CLKBUF_READY
|
|
/* Enable MPHY 26MHz ref clock */
|
|
clk_buf_ctrl(CLK_BUF_UFS, true);
|
|
ufshcd_writel(hba, 0, REG_UFS_ADDR_XOUFS_ST);
|
|
#endif
|
|
/* Set regulator to turn on VA09 LDO */
|
|
ret = regulator_enable(reg_va09);
|
|
if (ret < 0) {
|
|
dev_info(hba->dev,
|
|
"%s: enalbe va09 fail, err = %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/* wait 200 us to stablize VA09 */
|
|
udelay(200);
|
|
|
|
/* Step 1: Set RG_VA09_ON to 1 */
|
|
mt_secure_call(MTK_SIP_KERNEL_UFS_CTL, 1, 1, 0, 0);
|
|
|
|
/* Step 2: release DA_MP_PLL_PWR_ON */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg | (0x1 << 11);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg & ~(0x1 << 10);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
|
|
/* Step 3: release DA_MP_PLL_ISO_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg & ~(0x1 << 9);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg & ~(0x1 << 8);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
|
|
/* Step 4: release DA_MP_CDR_PWR_ON */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg | (0x1 << 18);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg & ~(0x1 << 17);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
|
|
/* Step 5: release DA_MP_CDR_ISO_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg & ~(0x1 << 20);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg & ~(0x1 << 19);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
|
|
/* Step 6: release DA_MP_RX0_SQ_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = reg | (0x1 << 1);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = reg & ~(0x1);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
|
|
/* Delay 1us to wait DIFZ stable */
|
|
udelay(1);
|
|
|
|
/* Step 7: release DIFZ */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA09C);
|
|
reg = reg & ~(0x1 << 18);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA09C);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ufs_mtk_pltfrm_suspend(struct ufs_hba *hba)
|
|
{
|
|
int ret = 0;
|
|
u32 reg;
|
|
|
|
/* Step 1: force DIFZ */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA09C);
|
|
reg = reg | (0x1 << 18);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA09C);
|
|
|
|
/* Step 2: force DA_MP_RX0_SQ_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = reg | (0x1);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
reg = reg & ~(0x1 << 1);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xA0AC);
|
|
|
|
/* Step 3: force DA_MP_CDR_ISO_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg | (0x1 << 19);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg | (0x1 << 20);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
|
|
/* Step 4: force DA_MP_CDR_PWR_ON */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg | (0x1 << 17);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
reg = reg & ~(0x1 << 18);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0xB044);
|
|
|
|
/* Step 5: force DA_MP_PLL_ISO_EN */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg | (0x1 << 8);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg | (0x1 << 9);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
|
|
/* Step 6: force DA_MP_PLL_PWR_ON */
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg | (0x1 << 10);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = readl(ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
reg = reg & ~(0x1 << 11);
|
|
writel(reg, ufs_mtk_mmio_base_ufs_mphy + 0x008C);
|
|
|
|
/* Step 7: Set RG_VA09_ON to 0 */
|
|
mt_secure_call(MTK_SIP_KERNEL_UFS_CTL, 1, 0, 0, 0);
|
|
|
|
/* delay awhile to satisfy T_HIBERNATE */
|
|
mdelay(15);
|
|
|
|
#ifdef CLKBUF_READY
|
|
/* Disable MPHY 26MHz ref clock in H8 mode */
|
|
clk_buf_ctrl(CLK_BUF_UFS, false);
|
|
ufshcd_writel(hba, 0, REG_UFS_ADDR_XOUFS_ST);
|
|
#endif
|
|
if (ufs_mtk_hba->curr_dev_pwr_mode != UFS_ACTIVE_PWR_MODE)
|
|
spm_resource_req(SPM_RESOURCE_USER_UFS, SPM_RESOURCE_RELEASE);
|
|
|
|
/* Set regulator to turn off VA09 LDO */
|
|
ret = regulator_disable(reg_va09);
|
|
if (ret < 0) {
|
|
dev_info(hba->dev,
|
|
"%s: disalbe va09 fail, err = %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
#if 0
|
|
/* TEST ONLY: emulate UFSHCI power off by HCI SW reset */
|
|
ufs_mtk_pltfrm_host_sw_rst(hba, SW_RST_TARGET_UFSHCI);
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
|