threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __I2C_CHARGER_RT9458_H
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#define __I2C_CHARGER_RT9458_H
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struct rt9458_platform_data {
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const char *chg_name;
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u32 ichg;
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u32 aicr;
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u32 mivr;
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u32 ieoc;
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u32 voreg;
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u32 vmreg;
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int intr_gpio;
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u8 enable_te:1;
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u8 enable_eoc_shdn:1;
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};
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enum rt9458_chg_stat {
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RT9458_CHG_STAT_READY = 0,
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RT9458_CHG_STAT_PROGRESS,
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RT9458_CHG_STAT_DONE,
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RT9458_CHG_STAT_FAULT,
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RT9458_CHG_STAT_MAX,
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};
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static const char *rt9458_chg_stat_name[RT9458_CHG_STAT_MAX] = {
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"ready", "progress", "done", "fault",
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};
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#define RT9458_REG_CTRL1 (0x00)
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#define RT9458_REG_CTRL2 (0x01)
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#define RT9458_REG_CTRL3 (0x02)
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#define RT9458_REG_DEVID (0x03)
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#define RT9458_REG_CTRL4 (0x04)
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#define RT9458_REG_CTRL5 (0x05)
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#define RT9458_REG_CTRL6 (0x06)
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#define RT9458_REG_CTRL7 (0x07)
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#define RT9458_REG_IRQ1 (0x08)
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#define RT9458_REG_IRQ2 (0x09)
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#define RT9458_REG_IRQ3 (0x0A)
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#define RT9458_REG_MASK1 (0x0B)
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#define RT9458_REG_MASK2 (0x0C)
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#define RT9458_REG_MASK3 (0x0D)
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#define RT9458_REG_CTRL8 (0x11)
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#define RT9458_IRQ_REGNUM (RT9458_REG_IRQ3 - RT9458_REG_IRQ1 + 1)
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enum {
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RT9458_IRQ_BATAB = 0,
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RT9458_IRQ_VINOVPI = 6,
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RT9458_IRQ_TSDI,
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RT9458_IRQ_CHMIVRI = 8,
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RT9458_IRQ_CHTREGI,
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RT9458_IRQ_CH32MI,
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RT9458_IRQ_CHRCHGI,
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RT9458_IRQ_CHTERMI,
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RT9458_IRQ_CHBATOVI,
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RT9458_IRQ_CHRVPI = 15,
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RT9458_IRQ_BST32SI = 19,
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RT9458_IRQ_BSTLOWVI = 21,
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RT9458_IRQ_BSTOLI,
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RT9458_IRQ_BSTVINOVI,
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RT9458_IRQ_MAX,
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};
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/* RT9458_REG_CTRL1 : 0x00 */
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#define RT9458_STAT_MASK (0x30)
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#define RT9458_STAT_SHFT (4)
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/* RT9458_REG_CTRL2 : 0x01 */
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#define RT9458_OPA_MASK (0x01)
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#define RT9458_TESHDN_MASK (0x20)
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#define RT9458_TERM_MASK (0x08)
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#define RT9458_IAICR_MASK (0xc0)
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#define RT9458_IAICR_SHFT (6)
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#define RT9458_IAICRINT_MASK (0x04)
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#define RT9458_HZ_MASK (0x02)
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/* RT9458_REG_CTRL3 : 0x02 */
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#define RT9458_VOREG_MASK (0xfc)
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#define RT9458_VOREG_SHFT (2)
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#define RT9458_VOREG_MAXVAL (0x2f)
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/* RT9458_REG_CTRL5 : 0x05 */
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#define RT9458_TMREN_MASK (0x80)
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#define RT9458_IEOC_MASK (0x07)
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#define RT9458_IEOC_SHFT (0)
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#define RT9458_IEOC_MAXVAL (7)
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/* RT9458_REG_CTRL6 : 0x06 */
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#define RT9458_IAICRSEL_MASK (0x80)
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#define RT9458_ICHG_MASK (0x70)
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#define RT9458_ICHG_SHFT (4)
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#define RT9458_ICHG_MAXVAL (7)
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/* RT9458_REG_CTRL7 : 0x07 */
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#define RT9458_CHGEN_MASK (0x10)
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#define RT9458_VMREG_MASK (0x0f)
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#define RT9458_VMREG_SHFT (0)
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#define RT9458_VMREG_MAXVAL (0x0c)
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/* RT9458_REG_CTRL8 : 0x11 */
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#define RT9458_MIVR_MASK (0x70)
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#define RT9458_MIVR_SHFT (4)
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#define RT9458_MIVR_MAXVAL (6)
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#endif /* #ifndef __I2C_CHARGER_RT9458_H */
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