threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XGENE_ENET_SGMAC_H__
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#define __XGENE_ENET_SGMAC_H__
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#define PHY_ADDR(src) (((src)<<8) & GENMASK(12, 8))
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#define REG_ADDR(src) ((src) & GENMASK(4, 0))
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#define PHY_CONTROL(src) ((src) & GENMASK(15, 0))
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#define LINK_SPEED(src) (((src) & GENMASK(11, 10)) >> 10)
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#define INT_PHY_ADDR 0x1e
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#define SGMII_TBI_CONTROL_ADDR 0x44
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#define SGMII_CONTROL_ADDR 0x00
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#define SGMII_STATUS_ADDR 0x04
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#define SGMII_BASE_PAGE_ABILITY_ADDR 0x14
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#define AUTO_NEG_COMPLETE BIT(5)
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#define LINK_STATUS BIT(2)
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#define LINK_UP BIT(15)
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#define MPA_IDLE_WITH_QMI_EMPTY BIT(12)
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#define SG_RX_DV_GATE_REG_0_ADDR 0x05fc
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#define SGMII_EN 0x1
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enum xgene_phy_speed {
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PHY_SPEED_10,
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PHY_SPEED_100,
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PHY_SPEED_1000
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};
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extern const struct xgene_mac_ops xgene_sgmac_ops;
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extern const struct xgene_port_ops xgene_sgport_ops;
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#endif /* __XGENE_ENET_SGMAC_H__ */
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