threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
275 lines
10 KiB
C
275 lines
10 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MSDC_CUST_MT6768_H_
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#define _MSDC_CUST_MT6768_H_
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#ifdef CONFIG_FPGA_EARLY_PORTING
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#define FPGA_PLATFORM
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#else
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/* #define MTK_MSDC_BRINGUP_DEBUG */
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#endif
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#include <dt-bindings/mmc/mt6768-msdc.h>
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/* #define CONFIG_MTK_MSDC_BRING_UP_BYPASS */
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#if !defined(FPGA_PLATFORM)
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#include <dt-bindings/clock/mt6768-clk.h>
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#endif
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#ifndef CONFIG_MTK_MSDC_BRING_UP_BYPASS
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#include <mtk_spm_resource_req.h>
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#endif
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/**************************************************************/
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/* Section 1: Device Tree */
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/**************************************************************/
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/* Names used for device tree lookup */
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#define DT_COMPATIBLE_NAME "mediatek,msdc"
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#define MSDC0_CLK_NAME "msdc0-clock"
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#if defined(CONFIG_MTK_HW_FDE) || defined(CONFIG_MMC_CRYPTO)
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#define MSDC0_AES_CLK_NAME "msdc0-aes-clock"
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#endif
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#define MSDC0_HCLK_NAME "msdc0-hclock"
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#define MSDC1_CLK_NAME "msdc1-clock"
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#define MSDC1_HCLK_NAME "msdc1-hclock"
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#define MSDC0_IOCFG_NAME "mediatek,io_cfg_tl"
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#define MSDC1_IOCFG_NAME "mediatek,io_cfg_lb"
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/**************************************************************/
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/* Section 2: Power */
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/**************************************************************/
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#define SD_POWER_DEFAULT_ON (0)
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#if !defined(FPGA_PLATFORM)
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#include <mt-plat/upmu_common.h>
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#define REG_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_ADDR
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#define REG_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_ADDR
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#define REG_VEMC_EN PMIC_RG_LDO_VEMC_EN_ADDR
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#define REG_VIO18_VOSEL_CAL PMIC_RG_VIO18_VOCAL_ADDR
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/* vio18 have no REG_VIO18_VOSEL, so not dump. */
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#define REG_VIO18_EN PMIC_RG_LDO_VIO18_EN_ADDR
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#define REG_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_ADDR
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#define REG_VMC_VOSEL PMIC_RG_VMC_VOSEL_ADDR
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#define REG_VMC_EN PMIC_RG_LDO_VMC_EN_ADDR
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#define REG_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_ADDR
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#define REG_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_ADDR
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#define REG_VMCH_EN PMIC_RG_LDO_VMCH_EN_ADDR
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#define MASK_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_MASK
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#define SHIFT_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_SHIFT
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#define FIELD_VEMC_VOSEL_CAL (MASK_VEMC_VOSEL_CAL << SHIFT_VEMC_VOSEL_CAL)
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#define MASK_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_MASK
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#define SHIFT_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_SHIFT
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#define FIELD_VEMC_VOSEL (MASK_VEMC_VOSEL << SHIFT_VEMC_VOSEL)
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#define MASK_VEMC_EN PMIC_RG_LDO_VEMC_EN_MASK
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#define SHIFT_VEMC_EN PMIC_RG_LDO_VEMC_EN_SHIFT
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#define FIELD_VEMC_EN (MASK_VEMC_EN << SHIFT_VEMC_EN)
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#define MASK_VIO18_VOSEL_CAL PMIC_RG_VIO18_VOCAL_MASK
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#define SHIFT_VIO18_VOSEL_CAL PMIC_RG_VIO18_VOCAL_SHIFT
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#define FIELD_VIO18_VOSEL_CAL (MASK_VIO18_VOSEL_CAL << SHIFT_VIO18_VOSEL_CAL)
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#define MASK_VIO18_EN PMIC_RG_LDO_VIO18_EN_MASK
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#define SHIFT_VIO18_EN PMIC_RG_LDO_VIO18_EN_SHIFT
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#define FIELD_VIO18_EN (MASK_VIO18_EN << SHIFT_VIO18_EN)
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#define MASK_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_MASK
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#define SHIFT_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_SHIFT
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#define FIELD_VMC_VOSEL_CAL (MASK_VMC_VOSEL_CAL << SHIFT_VMC_VOSEL_CAL)
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#define MASK_VMC_VOSEL PMIC_RG_VMC_VOSEL_MASK
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#define SHIFT_VMC_VOSEL PMIC_RG_VMC_VOSEL_SHIFT
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#define FIELD_VMC_VOSEL (MASK_VMC_VOSEL << SHIFT_VMC_VOSEL)
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#define MASK_VMC_EN PMIC_RG_LDO_VMC_EN_MASK
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#define SHIFT_VMC_EN PMIC_RG_LDO_VMC_EN_SHIFT
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#define FIELD_VMC_EN (MASK_VMC_EN << SHIFT_VMC_EN)
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#define MASK_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_MASK
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#define SHIFT_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_SHIFT
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#define FIELD_VMCH_VOSEL_CAL (MASK_VMCH_VOSEL_CAL << SHIFT_VMCH_VOSEL_CAL)
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#define MASK_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_MASK
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#define SHIFT_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_SHIFT
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#define FIELD_VMCH_VOSEL (MASK_VMCH_VOSEL << SHIFT_VMCH_VOSEL)
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#define MASK_VMCH_EN PMIC_RG_LDO_VMCH_EN_MASK
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#define SHIFT_VMCH_EN PMIC_RG_LDO_VMCH_EN_SHIFT
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#define FIELD_VMCH_EN (MASK_VMCH_EN << SHIFT_VMCH_EN)
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#define VEMC_VOSEL_3V (11)
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#define VEMC_VOSEL_3V3 (13)
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#define VMC_VOSEL_1V8 (4)
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#define VMC_VOSEL_2V8 (9)
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#define VMC_VOSEL_3V (11)
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#define VMCH_VOSEL_3V (11)
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#define VMCH_VOSEL_3V3 (13)
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#define REG_VCORE_VOSEL_SW PMIC_RG_BUCK_VCORE_VOSEL_ADDR
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#define VCORE_VOSEL_SW_MASK PMIC_RG_BUCK_VCORE_VOSEL_MASK
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#define VCORE_VOSEL_SW_SHIFT PMIC_RG_BUCK_VCORE_VOSEL_SHIFT
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#define REG_VIO_VOCAL_SW PMIC_RG_VIO18_VOCAL_ADDR
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#define VIO_VOCAL_SW_MASK PMIC_RG_VIO18_VOCAL_MASK
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#define VIO_VOCAL_SW_SHIFT PMIC_RG_VIO18_VOCAL_SHIFT
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#endif
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#define EMMC_VOL_ACTUAL VOL_3000
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#define SD_VOL_ACTUAL VOL_3000
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/**************************************************************/
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/* Section 3: Clock */
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/**************************************************************/
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#define MSDCPLL_FREQ 800000000
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/* list the other value by clock owners' clock table doc if needed */
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#define MSDC0_SRC_0 260000
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#define MSDC0_SRC_1 (MSDCPLL_FREQ/2)
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#define MSDC1_SRC_0 260000
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#define MSDC1_SRC_1 208000000
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#define MSDC1_SRC_2 (MSDCPLL_FREQ/4)
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#define MSDC3_SRC_0 260000
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#define MSDC3_SRC_1 208000000
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#define MSDC3_SRC_2 (MSDCPLL_FREQ/2)
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#define MSDC3_SRC_3 156000000
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#define MSDC3_SRC_4 182000000
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#define MSDC3_SRC_5 312000000
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#define MSDC3_SRC_6 364000000
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#define MSDC3_SRC_7 (MSDCPLL_FREQ/4)
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#define MSDC_SRC_FPGA 12000000
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/**************************************************************/
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/* Section 4: GPIO and Pad */
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/**************************************************************/
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/*--------------------------------------------------------------------------*/
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/* MSDC0~1 GPIO and IO Pad Configuration Base */
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/*--------------------------------------------------------------------------*/
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/* 0x10005000 */
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#define MSDC_GPIO_BASE gpio_base
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/* 0x10002E00 */
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#define MSDC0_IO_PAD_BASE (msdc_io_cfg_bases[0])
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/* 0x10002400 */
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#define MSDC1_IO_PAD_BASE (msdc_io_cfg_bases[1])
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/*--------------------------------------------------------------------------*/
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/* MSDC GPIO Related Register */
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/*--------------------------------------------------------------------------*/
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/* MSDC0 */
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#define MSDC0_GPIO_MODE0 (MSDC_GPIO_BASE + 0x3f0)
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#define MSDC0_GPIO_MODE1 (MSDC_GPIO_BASE + 0x400)
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#define MSDC0_GPIO_IES (MSDC0_IO_PAD_BASE + 0x10)
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#define MSDC0_GPIO_SMT (MSDC0_IO_PAD_BASE + 0x60)
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#define MSDC0_GPIO_TDSEL (MSDC0_IO_PAD_BASE + 0x70)
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#define MSDC0_GPIO_RDSEL (MSDC0_IO_PAD_BASE + 0x50)
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#define MSDC0_GPIO_DRV (MSDC0_IO_PAD_BASE + 0)
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#define MSDC0_GPIO_PUPD (MSDC0_IO_PAD_BASE + 0x20)
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#define MSDC0_GPIO_R0 (MSDC0_IO_PAD_BASE + 0x30)
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#define MSDC0_GPIO_R1 (MSDC0_IO_PAD_BASE + 0x40)
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/* MSDC1 */
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#define MSDC1_GPIO_MODE0 (MSDC_GPIO_BASE + 0x440)
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#define MSDC1_GPIO_MODE1 (MSDC_GPIO_BASE + 0x450)
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#define MSDC1_GPIO_IES (MSDC1_IO_PAD_BASE + 0x10)
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#define MSDC1_GPIO_SMT (MSDC1_IO_PAD_BASE + 0x80)
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#define MSDC1_GPIO_TDSEL (MSDC1_IO_PAD_BASE + 0xa0)
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#define MSDC1_GPIO_RDSEL (MSDC1_IO_PAD_BASE + 0x60)
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#define MSDC1_GPIO_DRV (MSDC1_IO_PAD_BASE + 0)
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#define MSDC1_GPIO_SR (MSDC1_IO_PAD_BASE + 0x90)
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#define MSDC1_GPIO_PUPD (MSDC1_IO_PAD_BASE + 0x30)
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#define MSDC1_GPIO_R0 (MSDC1_IO_PAD_BASE + 0x40)
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#define MSDC1_GPIO_R1 (MSDC1_IO_PAD_BASE + 0x50)
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/**************************************************************/
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/* Section 5: Adjustable Driver Parameter */
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/**************************************************************/
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#define HOST_MAX_BLKSZ (2048)
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#define MSDC_OCR_AVAIL\
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(MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 \
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| MMC_VDD_31_32 | MMC_VDD_32_33)
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/* data timeout counter. 1048576 * 3 sclk. */
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#define DEFAULT_DTOC (3)
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#define MAX_DMA_CNT (4 * 1024 * 1024)
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/* a WIFI transaction may be 50K */
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#define MAX_DMA_CNT_SDIO (0xFFFFFFFF - 255)
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/* a LTE transaction may be 128K */
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#define MAX_HW_SGMTS (MAX_BD_NUM)
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#define MAX_PHY_SGMTS (MAX_BD_NUM)
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#define MAX_SGMT_SZ (MAX_DMA_CNT)
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#define MAX_SGMT_SZ_SDIO (MAX_DMA_CNT_SDIO)
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#define HOST_MAX_NUM (2)
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#ifdef CONFIG_PWR_LOSS_MTK_TEST
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#define MAX_REQ_SZ (512 * 65536)
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#else
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#define MAX_REQ_SZ (512 * 1024)
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#endif
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#ifdef FPGA_PLATFORM
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#define HOST_MAX_MCLK (200000000)
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#else
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#define HOST_MAX_MCLK (200000000)
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#endif
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#define HOST_MIN_MCLK (260000)
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/* SD card, bad card handling settings */
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/* if continuous data timeout reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_DATA_TIMEOUT_CONTINUOUS (100)
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/* if continuous power cycle fail reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_POWER_CYCLE_FAIL_CONTINUOUS (3)
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/* sdcard esd recovery */
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/* power reset sdcard when sdcard hang from esd */
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#define SDCARD_ESD_RECOVERY
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/* #define MSDC_HQA */
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/* #define SDIO_HQA */
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/**************************************************************/
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/* Section 6: BBChip-depenent Tunnig Parameter */
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/**************************************************************/
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#define EMMC_MAX_FREQ_DIV 4 /* lower frequence to 12.5M */
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#define MSDC_CLKTXDLY 0
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#define MSDC0_DDR50_DDRCKD 1 /* FIX ME: may be removed */
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#define VOL_CHG_CNT_DEFAULT_VAL 0x1F4 /* =500 */
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/* hw diff: 0xB0[0]=1 */
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#define MSDC_PB0_DEFAULT_VAL 0x403C0007
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#define MSDC_PB1_DEFAULT_VAL 0xFFFA0349
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#define MSDC_PB2_DEFAULT_RESPWAITCNT 0x3
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#define MSDC_PB2_DEFAULT_RESPSTENSEL 0x1
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#define MSDC_PB2_DEFAULT_CRCSTSENSEL 0x1
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#endif /* _MSDC_CUST_MT6768_H_ */
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