threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __CLATM_INITCFG_H__
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#define __CLATM_INITCFG_H__
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#define CLATM_SET_INIT_CFG (1)
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#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
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#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
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#define CLATM_INIT_CFG_0_FIRST_STEP (3960)
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#define CLATM_INIT_CFG_0_THETA_RISE (2)
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#define CLATM_INIT_CFG_0_THETA_FALL (8)
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#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
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#define CLATM_INIT_CFG_0_MIN_CPU_PWR (500)
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#define CLATM_INIT_CFG_0_MAX_CPU_PWR (3960)
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#define CLATM_INIT_CFG_0_MIN_GPU_PWR (300)
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#define CLATM_INIT_CFG_0_MAX_GPU_PWR (2000)
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#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
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#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
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#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
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#define CLATM_INIT_CFG_1_THETA_RISE (2)
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#define CLATM_INIT_CFG_1_THETA_FALL (8)
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#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
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#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
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#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
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#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
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#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
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#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
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#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
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#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
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#define CLATM_INIT_CFG_2_THETA_RISE (2)
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#define CLATM_INIT_CFG_2_THETA_FALL (8)
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#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
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#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
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#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
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#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
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#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
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#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
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#define CLATM_INIT_CFG_CATM (2)
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#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
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#define CLATM_INIT_CFG_PHPB_CPU_TP (50)
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#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
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#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
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#define CLATM_INIT_HRTIMER_POLLING_DELAY (50)
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#define CLATM_USE_MIN_CPU_OPP (1)
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#define CLCTM_TARGET_TJ (85000)
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#define CLCTM_TPCB_1 (47000)
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#define CLCTM_TPCB_2 (51000)
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#define CLCTM_EXIT_TJ (CLCTM_TARGET_TJ - 10000)
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#define CLCTM_AE (CLCTM_TARGET_TJ)
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#define CLCTM_BE (0)
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#define CLCTM_AX (CLCTM_EXIT_TJ)
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#define CLCTM_BX (0)
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#define CLCTM_TT_HIGH (500)
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#define CLCTM_TT_LOW (500)
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#define CLCTM_STEADY_TTJ_DELTA (13500)
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#define CLATM_CONFIGURABLE_TIMER
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#define POLLING_TRIP_TEMP0 55000
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#define POLLING_TRIP_TEMP1 45000
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#define POLLING_TRIP_TEMP2 40000
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#define POLLING_FACTOR0 10
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#define POLLING_FACTOR1 2
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#define POLLING_FACTOR2 4
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#endif /* __CLATM_INITCFG_H__ */
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