threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
137 lines
5.5 KiB
C
137 lines
5.5 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __SSPM_MBOX_PIN_H__
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#define __SSPM_MBOX_PIN_H__
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#define SSPM_MBOX_TOTAL 5
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/* definition of slot size for OUT PINs */
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/* the following will use mbox 0 */
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#define IPIS_C_PPM_OUT_SIZE 7
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#define IPIS_C_QOS_OUT_SIZE 6
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#define IPIS_C_PMIC_OUT_SIZE 5
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#define IPIS_C_MET_OUT_SIZE 4
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#define IPIS_C_THERMAL_OUT_SIZE 4
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#define IPIS_C_GPU_DVFS_OUT_SIZE 4
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#define IPIS_C_GPU_PM_OUT_SIZE 2
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/* the following will use mbox 1 */
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#define IPIS_C_PLATFORM_OUT_SIZE 3
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#define IPIS_C_SMI_OUT_SIZE 3
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#define IPIS_C_CM_OUT_SIZE 2
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#define IPIS_C_SLBC_OUT_SIZE 2
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#define IPIS_C_SPM_SUSPEND_OUT_SIZE 8
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#define IPIR_C_MET_OUT_SIZE 1
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#define IPIR_C_GPU_DVFS_OUT_SIZE 1
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#define IPIR_C_PLATFORM_OUT_SIZE 1
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#define IPIR_C_SLBC_OUT_SIZE 1
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/* definition of slot offset for OUT PINs */
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/* the following will use mbox 0 */
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#define IPIS_C_PPM_OUT_OFFSET 0
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#define IPIS_C_QOS_OUT_OFFSET (IPIS_C_PPM_OUT_OFFSET \
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+ IPIS_C_PPM_OUT_SIZE)
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#define IPIS_C_PMIC_OUT_OFFSET (IPIS_C_QOS_OUT_OFFSET \
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+ IPIS_C_QOS_OUT_SIZE)
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#define IPIS_C_MET_OUT_OFFSET (IPIS_C_PMIC_OUT_OFFSET \
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+ IPIS_C_PMIC_OUT_SIZE)
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#define IPIS_C_THERMAL_OUT_OFFSET (IPIS_C_MET_OUT_OFFSET \
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+ IPIS_C_MET_OUT_SIZE)
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#define IPIS_C_GPU_DVFS_OUT_OFFSET (IPIS_C_THERMAL_OUT_OFFSET \
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+ IPIS_C_THERMAL_OUT_SIZE)
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#define IPIS_C_GPU_PM_OUT_OFFSET (IPIS_C_GPU_DVFS_OUT_OFFSET \
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+ IPIS_C_GPU_DVFS_OUT_SIZE)
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/* the following will use mbox 1 */
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#define IPIS_C_PLATFORM_OUT_OFFSET 0
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#define IPIS_C_SMI_OUT_OFFSET (IPIS_C_PLATFORM_OUT_OFFSET \
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+ IPIS_C_PLATFORM_OUT_SIZE)
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#define IPIS_C_CM_OUT_OFFSET (IPIS_C_SMI_OUT_OFFSET \
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+ IPIS_C_SMI_OUT_SIZE)
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#define IPIS_C_SLBC_OUT_OFFSET (IPIS_C_CM_OUT_OFFSET \
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+ IPIS_C_CM_OUT_SIZE)
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#define IPIS_C_SPM_SUSPEND_OUT_OFFSET (IPIS_C_SLBC_OUT_OFFSET \
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+ IPIS_C_SLBC_OUT_SIZE)
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#define IPIR_C_MET_OUT_OFFSET (IPIS_C_SPM_SUSPEND_OUT_OFFSET \
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+ IPIS_C_SPM_SUSPEND_OUT_SIZE)
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#define IPIR_C_GPU_DVFS_OUT_OFFSET (IPIR_C_MET_OUT_OFFSET \
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+ IPIR_C_MET_OUT_SIZE)
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#define IPIR_C_PLATFORM_OUT_OFFSET (IPIR_C_GPU_DVFS_OUT_OFFSET \
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+ IPIR_C_GPU_DVFS_OUT_SIZE)
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#define IPIR_C_SLBC_OUT_OFFSET (IPIR_C_PLATFORM_OUT_OFFSET \
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+ IPIR_C_PLATFORM_OUT_SIZE)
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/* definition of slot size for IN PINs */
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/* the following will use mbox 2 */
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#define IPIR_I_QOS_IN_SIZE 6
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#define IPIR_C_MET_IN_SIZE 4
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#define IPIR_C_GPU_DVFS_IN_SIZE 4
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#define IPIR_C_PLATFORM_IN_SIZE 3
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#define IPIR_C_SLBC_IN_SIZE 2
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#define IPIS_C_PPM_IN_SIZE 1
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#define IPIS_C_QOS_IN_SIZE 1
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#define IPIS_C_PMIC_IN_SIZE 1
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#define IPIS_C_MET_IN_SIZE 1
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#define IPIS_C_THERMAL_IN_SIZE 1
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#define IPIS_C_GPU_DVFS_IN_SIZE 1
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#define IPIS_C_GPU_PM_IN_SIZE 1
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#define IPIS_C_PLATFORM_IN_SIZE 1
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#define IPIS_C_SMI_IN_SIZE 1
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#define IPIS_C_CM_IN_SIZE 1
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#define IPIS_C_SLBC_IN_SIZE 1
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#define IPIS_C_SPM_SUSPEND_IN_SIZE 1
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/* definition of slot offset for IN PINs */
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/* the following will use mbox 2 */
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#define IPIR_I_QOS_IN_OFFSET 0
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#define IPIR_C_MET_IN_OFFSET (IPIR_I_QOS_IN_OFFSET \
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+ IPIR_I_QOS_IN_SIZE)
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#define IPIR_C_GPU_DVFS_IN_OFFSET (IPIR_C_MET_IN_OFFSET \
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+ IPIR_C_MET_IN_SIZE)
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#define IPIR_C_PLATFORM_IN_OFFSET (IPIR_C_GPU_DVFS_IN_OFFSET \
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+ IPIR_C_GPU_DVFS_IN_SIZE)
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#define IPIR_C_SLBC_IN_OFFSET (IPIR_C_PLATFORM_IN_OFFSET \
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+ IPIR_C_PLATFORM_IN_SIZE)
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#define IPIS_C_PPM_IN_OFFSET (IPIR_C_SLBC_IN_OFFSET \
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+ IPIR_C_SLBC_IN_SIZE)
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#define IPIS_C_QOS_IN_OFFSET (IPIS_C_PPM_IN_OFFSET \
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+ IPIS_C_PPM_IN_SIZE)
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#define IPIS_C_PMIC_IN_OFFSET (IPIS_C_QOS_IN_OFFSET \
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+ IPIS_C_QOS_IN_SIZE)
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#define IPIS_C_MET_IN_OFFSET (IPIS_C_PMIC_IN_OFFSET \
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+ IPIS_C_PMIC_IN_SIZE)
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#define IPIS_C_THERMAL_IN_OFFSET (IPIS_C_MET_IN_OFFSET \
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+ IPIS_C_MET_IN_SIZE)
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#define IPIS_C_GPU_DVFS_IN_OFFSET (IPIS_C_THERMAL_IN_OFFSET \
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+ IPIS_C_THERMAL_IN_SIZE)
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#define IPIS_C_GPU_PM_IN_OFFSET (IPIS_C_GPU_DVFS_IN_OFFSET \
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+ IPIS_C_GPU_DVFS_IN_SIZE)
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#define IPIS_C_PLATFORM_IN_OFFSET (IPIS_C_GPU_PM_IN_OFFSET \
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+ IPIS_C_GPU_PM_IN_SIZE)
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#define IPIS_C_SMI_IN_OFFSET (IPIS_C_PLATFORM_IN_OFFSET \
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+ IPIS_C_PLATFORM_IN_SIZE)
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#define IPIS_C_CM_IN_OFFSET (IPIS_C_SMI_IN_OFFSET \
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+ IPIS_C_SMI_IN_SIZE)
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#define IPIS_C_SLBC_IN_OFFSET (IPIS_C_CM_IN_OFFSET \
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+ IPIS_C_CM_IN_SIZE)
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#define IPIS_C_SPM_SUSPEND_IN_OFFSET (IPIS_C_SLBC_IN_OFFSET \
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+ IPIS_C_SLBC_IN_SIZE)
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#define SHAREMBOX_NO_MCDI 3
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#define SHAREMBOX_OFFSET_MCDI 0
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#define SHAREMBOX_SIZE_MCDI 20
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#define SHAREMBOX_OFFSET_TIMESTAMP (SHAREMBOX_OFFSET_MCDI \
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+ SHAREMBOX_SIZE_MCDI)
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#define SHAREMBOX_SIZE_TIMESTAMP 6
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#endif /* __SSPM_MBOX_PIN_H__ */
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