threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __SSPM_DEFINE_H__
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#define __SSPM_DEFINE_H__
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#include <linux/param.h> /* for HZ */
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#include <asm/arch_timer.h>
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#define SSPM_MBOX_MAX 5
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#define SSPM_MBOX_IN_IRQ_OFS 0x0
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#define SSPM_MBOX_OUT_IRQ_OFS 0x4
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#define SSPM_MBOX_SLOT_SIZE 0x4
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#define SSPM_CFG_OFS_SEMA 0x048
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#define SLOT_PER_MBOX 32
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#define MBOX_IN_IRQ_OFS 0x0
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#define MBOX_OUT_IRQ_OFS 0x4
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#define MBOX_SLOT_SIZE 0x4
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#define SSPM_PLT_SERV_SUPPORT (1)
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#define SSPM_LOGGER_SUPPORT (1)
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#define SSPM_LASTK_SUPPORT (0)
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#define SSPM_COREDUMP_SUPPORT (0)
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#define SSPM_EMI_PROTECTION_SUPPORT (1)
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/*
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* TimeSync v2
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* - Enabled if CONFIG_MTK_TIMER_TIMESYNC is defined.
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* - Timesync shall be trigered by timer module only, thus
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* SSPM_TIMESYNC_SUPPORT shall be disabled.
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*/
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#ifdef CONFIG_MTK_TIMER_TIMESYNC
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#define SSPM_TIMESYNC_SUPPORT (0)
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#else
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#define SSPM_TIMESYNC_SUPPORT (1)
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#endif
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#define TIMESYNC_TIMEOUT (60 * 60 * HZ)
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#define PLT_INIT 0x504C5401
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#define PLT_LOG_ENABLE 0x504C5402
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#define PLT_TIMESYNC_SYNC 0x504C5405
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#define PLT_TIMESYNC_SRAM_TEST 0x504C5406
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#define SSPM_MPU_REGION_ID 4
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#define mtk_timer_src_count(...) arch_counter_get_cntvct(__VA_ARGS__)
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struct plt_ipi_data_s {
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unsigned int cmd;
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union {
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struct {
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unsigned int phys;
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unsigned int size;
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} ctrl;
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struct {
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unsigned int enable;
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} logger;
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struct {
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unsigned int mode;
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} ts;
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} u;
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};
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#endif
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