threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/*****************************************************************************
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*
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*****************************************************************************/
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#ifndef MPU6050_H
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#define MPU6050_H
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#include <linux/ioctl.h>
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#define MPU6050_ACCESS_BY_GSE_I2C
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#ifdef MPU6050_ACCESS_BY_GSE_I2C
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/* mtk i2c not allow to probe two same address */
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#define MPU6050_I2C_SLAVE_ADDR (0xD2)
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#else
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#define MPU6050_I2C_SLAVE_ADDR 0xD0
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#endif
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/* MPU6050 Register Map (Please refer to MPU6050 Specifications) */
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#define MPU6050_REG_DEVID 0x75
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#define MPU6050_REG_FIFO_EN 0x23
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#define MPU6050_REG_AUX_VDD 0x01
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#define MPU6050_REG_SAMRT_DIV 0x19
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#define MPU6050_REG_CFG 0x1A
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/* full-scale range and sample rate, */
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#define MPU6050_REG_GYRO_CFG 0x1B
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#define MPU6050_REG_GYRO_XH 0x43
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#define MPU6050_REG_TEMPH 0x41
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#define MPU6050_REG_FIFO_CNTH 0x72
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#define MPU6050_REG_FIFO_CNTL 0x73
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#define MPU6050_REG_FIFO_DATA 0x74
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#define MPU6050_REG_FIFO_CTL 0x6A
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#define MPU6050_REG_PWR_CTL 0x6B
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#define MPU6050_REG_PWR_CTL2 0x6C
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/*MPU6050 Register Bit definitions*/
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/* insert the X Gyro data into FIFO */
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#define MPU6050_FIFO_GYROX_EN 0x40
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/* insert the Y Gyro data into FIFO */
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#define MPU6050_FIFO_GYROY_EN 0x20
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/* insert the Z Gyro data into FIFO */
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#define MPU6050_FIFO_GYROZ_EN 0x10
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/* disable VDD level for the secondary I2C bus clock and data lines */
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#define MPU6050_AUX_VDDIO_DIS 0x00
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/* for MPU6050_REG_CFG */
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/*
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* 0x05 captue the state of external frame sync
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* input pin to insert into LSB of registers
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*/
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#define MPU6050_EXT_SYNC 0x03
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#define MPU6050_SYNC_GYROX 0x02
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/* for MPU6050_REG_GYRO_CFG */
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/* set the full-scale range of the gyro sensors */
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#define MPU6050_FS_RANGE 0x03
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#define MPU6050_FS_1000 0x02
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#define MPU6050_FS_1000_LSB 33
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#define MPU6050_FS_MAX_LSB 131
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#define MPU6050_RATE_1K_LPFB_188HZ 0x01
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#define MPU6050_RATE_1K_LPFB_256HZ 0x00
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/* enable FIFO operation for sensor data */
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#define MPU6050_FIFO_EN 0x40
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/* reset FIFO function */
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#define MPU6050_FIFO_RST 0x40
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/* enable low power sleep mode */
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#define MPU6050_SLEEP 0x40
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#define MPU6050_BUFSIZE 60
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/* 1 rad = 180/PI degree, MAX_LSB = 131, */
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/* 180*131/PI = 7506 */
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#define DEGREE_TO_RAD 7506
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extern int MPU6050_gse_power(void);
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extern int MPU6050_gse_mode(void);
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#ifdef MPU6050_ACCESS_BY_GSE_I2C
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extern int MPU6050_hwmsen_read_block(u8 addr, u8 *buf, u8 len);
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extern int MPU6050_hwmsen_write_block(u8 addr, u8 *buf, u8 len);
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#endif
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#endif /* MPU6050_H */
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