threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
70 lines
3.2 KiB
C
70 lines
3.2 KiB
C
/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef _SCP_MBOX_LAYOUT_H_
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#define _SCP_MBOX_LAYOUT_H_
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#define SCP_MBOX_TOTAL 5
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/* core1 */
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/* definition of slot size for send PINs */
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#define PIN_OUT_SIZE_AUDIO_VOW_1 9 /* the following will use mbox 0 */
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/* definition of slot size for received PINs */
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#define PIN_IN_SIZE_AUDIO_VOW_ACK_1 2 /* the following will use mbox 0 */
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#define PIN_IN_SIZE_AUDIO_VOW_1 26 /* the following will use mbox 0 */
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/* core0 */
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/* definition of slot size for send PINs */
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#define PIN_OUT_SIZE_APCCCI_0 2 /* the following will use mbox 1 */
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#define PIN_OUT_SIZE_DVFS_SET_FREQ_0 1 /* the following will use mbox 1 */
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#define PIN_OUT_C_SIZE_SLEEP_0 1 /* the following will use mbox 1 */
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#define PIN_OUT_R_SIZE_SLEEP_0 1 /* the following will use mbox 1 */
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#define PIN_OUT_SIZE_TEST_0 1 /* the following will use mbox 1 */
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#define PIN_OUT_SIZE_AUDIO_ULTRA_SND_0 9 /* the following will use mbox 1 */
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/* definition of slot size for received PINs */
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#define PIN_IN_SIZE_APCCCI_0 2 /* the following will use mbox 1 */
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#define PIN_IN_SIZE_SCP_ERROR_INFO_0 10 /* the following will use mbox 1 */
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#define PIN_IN_SIZE_SCP_READY_0 1 /* the following will use mbox 1 */
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#define PIN_IN_SIZE_SCP_RAM_DUMP_0 2 /* the following will use mbox 1 */
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#define PIN_IN_SIZE_AUDIO_ULTRA_SND_0 5 /* the following will use mbox 1 */
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#define PIN_IN_SIZE_AUDIO_ULTRA_SND_ACK_0 2 /* the following will use mbox 1 */
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/* ============================================================ */
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/* core1 */
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/* definition of slot size for send PINs */
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#define PIN_OUT_SIZE_DVFS_SET_FREQ_1 1 /* the following will use mbox 3 */
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#define PIN_OUT_C_SIZE_SLEEP_1 1 /* the following will use mbox 3 */
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#define PIN_OUT_R_SIZE_SLEEP_1 1 /* the following will use mbox 3 */
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#define PIN_OUT_SIZE_TEST_1 1 /* the following will use mbox 3 */
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#define PIN_OUT_SIZE_LOGGER_CTRL 6 /* the following will use mbox 3 */
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#define PIN_OUT_SIZE_SCPCTL_1 2 /* the following will use mbox 3 */
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/* definition of slot size for received PINs */
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#define PIN_IN_SIZE_SCP_ERROR_INFO_1 10 /* the following will use mbox 3 */
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#define PIN_IN_SIZE_LOGGER_CTRL 6 /* the following will use mbox 3 */
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#define PIN_IN_SIZE_SCP_READY_1 1 /* the following will use mbox 3 */
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#define PIN_IN_SIZE_SCP_RAM_DUMP_1 2 /* the following will use mbox 3 */
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/* ============================================================ */
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/* this is mbox pool for 2 cores */
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#define PIN_OUT_SIZE_SCP_MPOOL 34 /* the following will use mbox 2,4 */
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#define PIN_IN_SIZE_SCP_MPOOL 30 /* the following will use mbox 2,4 */
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#define PIN_OUT_SIZE_CHRE_0 34
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#define PIN_OUT_SIZE_CHREX_0 14
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#define PIN_OUT_SIZE_SENSOR_0 14
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#define PIN_IN_SIZE_CHRE_0 14
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#define PIN_IN_SIZE_SENSOR_0 14
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#endif
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