threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
/*
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* drivers/misc/mediatek/pmic/mt6360/inc/mt6360_pmu_chg.h
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*
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* Copyright (C) 2018 Mediatek Technology Corp.
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* cy_huang <cy_huang@richtek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __MT6360_PMU_CHG_H
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#define __MT6360_PMU_CHG_H
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/* Define this macro if DCD timeout is supported */
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#define CONFIG_MT6360_DCDTOUT_SUPPORT
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struct mt6360_chg_platform_data {
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u32 ichg;
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u32 aicr;
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u32 mivr;
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u32 cv;
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u32 ieoc;
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u32 vrechg;
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u32 safety_timer;
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u32 ircmp_resistor;
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u32 ircmp_vclamp;
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u32 en_te;
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u32 en_wdt;
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u32 en_otg_wdt;
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u32 aicc_once;
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u32 post_aicc;
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u32 batoc_notify;
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const char *chg_name;
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};
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/* MT6360_PMU_CORE_CTRL2 : 0x06 */
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#define MT6360_MASK_SHIP_RST_DIS BIT(0)
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/* MT6360_PMU_CHG_CTRL1 : 0x11 */
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#define MT6360_MASK_FORCE_SLEEP BIT(3)
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#define MT6360_SHFT_FORCE_SLEEP (3)
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#define MT6360_MASK_HZ_EN BIT(2)
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#define MT6360_SHFT_HZ_EN (2)
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#define MT6360_MASK_OPA_MODE BIT(0)
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#define MT6360_SHFT_OPA_MODE (0)
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/* MT6360_PMU_CHG_CTRL2 : 0x12 */
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#define MT6360_MASK_SHIP_MODE BIT(7)
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#define MT6360_MASK_IINLMTSEL (0x0C)
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#define MT6360_SHFT_IINLMTSEL (2)
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#define MT6360_MASK_TE_EN BIT(4)
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#define MT6360_SHFT_TE_EN (4)
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#define MT6360_MASK_CFO_EN BIT(1)
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#define MT6360_SHFT_CFO_EN (1)
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#define MT6360_MASK_CHG_EN BIT(0)
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#define MT6360_SHFT_CHG_EN (0)
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/* MT6360_PMU_CHG_CTRL3 : 0x13 */
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#define MT6360_MASK_AICR (0xFC)
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#define MT6360_SHFT_AICR (2)
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#define MT6360_AICR_MAXVAL (0x3F)
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#define MT6360_MASK_ILIM_EN BIT(0)
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/* MT6360_PMU_CHG_CTRL4 : 0x14 */
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#define MT6360_MASK_VOREG (0xFE)
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#define MT6360_SHFT_VOREG (1)
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#define MT6360_VOREG_MAXVAL (0x51)
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/* MT6360_PMU_CHG_CTRL6 : 0x16 */
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#define MT6360_MASK_MIVR (0xFE)
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#define MT6360_SHFT_MIVR (1)
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#define MT6360_MIVR_MAXVAL (0x5F)
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/* MT6360_PMU_CHG_CTRL7 : 0x17 */
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#define MT6360_MASK_ICHG (0xFC)
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#define MT6360_SHFT_ICHG (2)
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#define MT6360_ICHG_MAXVAL (0x31)
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/* MT6360_PMU_CHG_CTRL9 : 0x19 */
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#define MT6360_MASK_IEOC (0xF0)
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#define MT6360_SHFT_IEOC (4)
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#define MT6360_IEOC_MAXVAL (0x0F)
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/* MT6360_PMU_CHG_AICC_RESULT : 0x21 */
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#define MT6360_MASK_RG_AICC_RESULT (0xFC)
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#define MT6360_SHFT_RG_AICC_RESULT (2)
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/* MT6360_PMU_CHG_CTRL10 : 0x1A */
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#define MT6360_MASK_OTG_OC (0x07)
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#define MT6360_SHFT_OTG_OC (0)
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#define MT6360_OTG_OC_MAXVAL (0x07)
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/* MT6360_PMU_CHG_CTRL12 : 0x1C */
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#define MT6360_MASK_TMR_EN BIT(1)
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#define MT6360_SHFT_TMR_EN (1)
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/* MT6360_PMU_CHG_CTRL13 : 0x1D */
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#define MT6360_MASK_CHG_WDT_EN BIT(7)
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/* MT6360_PMU_CHG_CTRL14 : 0x1E */
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#define MT6360_MASK_RG_EN_AICC BIT(7)
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#define MT6360_MASK_RG_AICC_ONCE BIT(2)
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/* MT6360_PMU_DEVICE_TYPE : 0x22 */
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#define MT6360_MASK_USBCHGEN BIT(7)
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#define MT6360_SHFT_USBCHGEN (7)
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#define MT6360_MASK_DCDTOUTEN BIT(6)
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#define MT6360_SHFT_DCDTOUTEN 6
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/* MT6360_PMU_USB_STATUS1 : 0x27 */
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#define MT6360_MASK_USB_STATUS (0x70)
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#define MT6360_SHFT_USB_STATUS (4)
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/* MT6360_PMU_CHG_CTRL16 : 0x2A */
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#define MT6360_MASK_AICC_VTH (0xFE)
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#define MT6360_SHFT_AICC_VTH (1)
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#define MT6360_AICC_VTH_MAXVAL (0x5F)
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/* MT6360_PMU_CHG_CTRL17 : 0x2B */
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#define MT6360_MASK_EN_PUMPX BIT(7)
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#define MT6360_SHFT_EN_PUMPX (7)
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#define MT6360_MASK_PUMPX_20_10 BIT(6)
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#define MT6360_SHFT_PUMPX_20_10 (6)
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#define MT6360_MASK_PUMPX_UP_DN BIT(5)
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#define MT6360_SHFT_PUMPX_UP_DN (5)
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#define MT6360_MASK_PUMPX_DEC (0x1F)
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#define MT6360_SHFT_PUMPX_DEC (0)
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#define MT6360_PUMPX_20_MAXVAL (0x1D)
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/* MT6360_PMU_CHG_CTRL18 : 0x2C */
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#define MT6360_MASK_BAT_COMP (0x38)
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#define MT6360_SHFT_BAT_COMP (3)
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#define MT6360_BAT_COMP_MAXVAL (0x07)
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#define MT6360_MASK_VCLAMP (0x7)
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#define MT6360_SHFT_VCLAMP (0)
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#define MT6360_VCLAMP_MAXVAL (0x07)
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/* MT6360_PMU_CHG_HIDDEN_CTRL2 : 0x31 */
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#define MT6360_MASK_EOC_RST BIT(7)
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#define MT6360_MASK_DISCHG BIT(2)
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#define MT6360_SHFT_DISCHG (2)
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/* MT6360_PMU_CHG_STAT : 0x4A */
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#define MT6360_MASK_CHG_STAT (0xC0)
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#define MT6360_SHFT_CHG_STAT (6)
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#define MT6360_MASK_CHG_BATSYSUV BIT(1)
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/* MT6360_PMU_TYPEC_OTP_CTRL: 0x51 */
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#define MT6360_MASK_TYPEC_OTP_SWEN BIT(2)
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#define MT6360_MASK_TYPEC_OTP_EN BIT(0)
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/* MT6360_PMU_ADC_CONFIG : 0x56 */
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#define MT6360_MASK_ZCV_EN BIT(6)
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#define MT6360_SHFT_ZCV_EN (6)
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/* MT6360_PMU_CHG_CTRL19 : 0x61 */
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#define MT6360_MASK_CHG_VIN_OVP_VTHSEL (0x60)
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#define MT6360_SHFT_CHG_VIN_OVP_VTHSEL (5)
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/* MT6360_PMU_FOD_CTRL : 0x65 */
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#define MT6360_MASK_FOD_SWEN BIT(7)
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/* MT6360_PMU_CHG_CTRL20 : 0x66 */
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#define MT6360_MASK_EN_SDI BIT(1)
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/* MT6360_PMU_USBID_CTRL1 : 0x6D */
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#define MT6360_MASK_USBID_EN BIT(7)
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#define MT6360_SHFT_ID_RPULSEL 5
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#define MT6360_MASK_ID_RPULSEL 0x60
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#define MT6360_MASK_ISTDET 0x1C
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#define MT6360_SHFT_ISTDET 2
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/* MT6360_PMU_USBID_CTRL2 : 0x6E */
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#define MT6360_MASK_IDTD 0xE0
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#define MT6360_MASK_USBID_FLOAT BIT(1)
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/* MT6360_PMU_FLED_EN : 0x7E */
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#define MT6360_MASK_STROBE_EN BIT(2)
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/* MT6360_PMU_CHG_STAT1 : 0xE0 */
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#define MT6360_MASK_PWR_RDY_EVT BIT(7)
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#define MT6360_SHFT_PWR_RDY_EVT (7)
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#define MT6360_MASK_MIVR_EVT BIT(6)
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#define MT6360_SHFT_MIVR_EVT (6)
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#define MT6360_MASK_CHG_TREG BIT(4)
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#define MT6360_SHFT_CHG_TREG (4)
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/* MT6360_PMU_CHG_STAT4 : 0xE3 */
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#define MT6360_MASK_CHG_TMRI BIT(3)
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#endif /* __MT6360_PMU_CHG_H */
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