threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __MT6691_REGULATOR_H
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#define __MT6691_REGULATOR_H
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#include <linux/mutex.h>
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#define MT6691_DRV_VERSION "1.0.0_MTK"
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struct mt6691_regulator_info {
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struct device *dev;
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struct i2c_client *i2c;
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struct mutex io_lock;
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#ifdef CONFIG_RT_REGMAP
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struct rt_regmap_device *regmap_dev;
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struct rt_regmap_properties *regmap_props;
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#endif /* #ifdef CONFIG_RT_REGMAP */
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struct regulator_dev *regulator;
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const struct regulator_chip *reg_chip;
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int id;
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int pin_sel;
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};
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/* pmic extbuck extern functions */
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extern int is_mt6691_exist(void);
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/* Custom MT6691_NAME */
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#define MT6691_NAME_0 "ext_buck_lp4"
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#define MT6691_NAME_1 "ext_buck_lp4x"
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#define MT6691_NAME_2 "ext_buck_vmddr"
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/* MT6691 operation register */
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#define MT6691_REG_VSEL0 (0x00)
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#define MT6691_REG_VSEL1 (0x01)
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#define MT6691_REG_CTRL1 (0x02)
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#define MT6691_REG_ID1 (0x03)
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#define MT6691_REG_ID2 (0x04)
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#define MT6691_REG_MONITOR (0x05)
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#define MT6691_REG_CTRL2 (0x06)
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#define MT6691_REG_CTRL3 (0x07)
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#define MT6691_REG_CTRL4 (0x08)
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/* Hidden mode */
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/* #define MT6691_REG_CTRL5 (0x09) */
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#if defined(MT6691_NAME_0)
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#define MT6691_CMPT_STR_0 "mediatek,ext_buck_lp4"
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#define MT6691_VSEL_0 MT6691_REG_VSEL0
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#define MT6691_CTRL_0 MT6691_REG_CTRL1
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#define MT6691_CTRL_BIT_0 0x01
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#define MT6691_EN_0 MT6691_REG_CTRL2
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#define MT6691_EN_BIT_0 0x01
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#endif
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#if defined(MT6691_NAME_1)
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#define MT6691_CMPT_STR_1 "mediatek,ext_buck_lp4x"
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#define MT6691_VSEL_1 MT6691_REG_VSEL1
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#define MT6691_CTRL_1 MT6691_REG_CTRL1
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#define MT6691_CTRL_BIT_1 0x02
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#define MT6691_EN_1 MT6691_REG_CTRL2
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#define MT6691_EN_BIT_1 0x02
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#endif
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#if defined(MT6691_NAME_2)
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#define MT6691_CMPT_STR_2 "mediatek,ext_buck_vmddr"
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#define MT6691_VSEL_2 MT6691_REG_VSEL0
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#define MT6691_CTRL_2 MT6691_REG_CTRL1
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#define MT6691_CTRL_BIT_2 0x01
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#define MT6691_EN_2 MT6691_REG_CTRL2
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#define MT6691_EN_BIT_2 0x01
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#endif
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#endif /*--__MT6691_REGULATOR_H--*/
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