threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
272 lines
7.9 KiB
C
272 lines
7.9 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MTK_PHY_NEW_H
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#define __MTK_PHY_NEW_H
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#define CONFIG_U3D_HAL_SUPPORT
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#ifdef CONFIG_U3D_HAL_SUPPORT
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#include "mu3d_hal_hw.h"
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#endif
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#ifdef CONFIG_U3D_HAL_SUPPORT
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#define REF_CK U3D_PHY_REF_CK
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#else
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#define REF_CK 25
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#endif
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/* include system library */
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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/* BASE ADDRESS DEFINE, should define this on ASIC */
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#define PHY_BASE 0x0
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#define SIFSLV_SPLLC_BASE (PHY_BASE+0x0)
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#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
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#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
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#define U2_PHY_BASE (PHY_BASE+0x800)
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#define U3_PHYD_BASE (PHY_BASE+0x900)
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#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
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#define U3_PHYA_BASE (PHY_BASE+0xb00)
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#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
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/*
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*0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
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*0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
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*0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
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*0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
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*0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
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*0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
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*0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
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*/
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/* TYPE DEFINE */
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#define PHY_UINT32 unsigned int
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#define PHY_INT32 int
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#define PHY_UINT16 unsigned short
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#define PHY_INT16 short
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#define PHY_UINT8 unsigned char
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#define PHY_INT8 char
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typedef PHY_UINT32 __bitwise PHY_LE32;
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#ifdef CONFIG_U3_PHY_AHB_SUPPORT
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#ifdef CONFIG_ARM64
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typedef u64 u3phy_addr_t;
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#define ALIGN_MASK 0xFFFFFFFFFFFFFFFC
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#else
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typedef u32 u3phy_addr_t;
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#define ALIGN_MASK 0xFFFFFFFC
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#endif
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#else
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typedef u32 u3phy_addr_t;
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#define ALIGN_MASK 0xFFFFFFFC
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#endif
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/* MACRO DEFINE */
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#define DRV_WriteReg32(addr, data) writel(data, (void __iomem *)addr)
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#define DRV_Reg32(addr) readl((void __iomem *)addr)
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/* CONSTANT DEFINE */
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#define PHY_FALSE 0
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#define PHY_TRUE 1
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/* #define DRV_MDELAY mdelay */
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#define DRV_MSLEEP msleep
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#define DRV_UDELAY udelay
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/* #define DRV_USLEEP usleep */
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/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
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PHY_INT32 U3PhyWriteReg32(u3phy_addr_t addr, PHY_UINT32 data);
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PHY_INT32 U3PhyReadReg32(u3phy_addr_t addr);
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PHY_INT32 U3PhyWriteReg8(u3phy_addr_t addr, PHY_UINT8 data);
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PHY_INT8 U3PhyReadReg8(u3phy_addr_t addr);
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/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
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PHY_INT32 U3PhyWriteField8(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
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PHY_INT32 U3PhyWriteField32(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
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PHY_INT32 U3PhyReadField8(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask);
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PHY_INT32 U3PhyReadField32(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask);
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struct u3phy_info {
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PHY_INT32 phy_version;
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PHY_INT32 phyd_version_addr;
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#ifdef CONFIG_PROJECT_PHY
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struct u2phy_reg_e *u2phy_regs_e;
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struct u3phya_reg_e *u3phya_regs_e;
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struct u3phya_da_reg_e *u3phya_da_regs_e;
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struct u3phyd_reg_e *u3phyd_regs_e;
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struct u3phyd_bank2_reg_e *u3phyd_bank2_regs_e;
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struct sifslv_chip_reg_e *sifslv_chip_regs_e;
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struct spllc_reg_e *spllc_regs_e;
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struct sifslv_fm_feg_e *sifslv_fm_regs_e;
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#else
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#ifdef CONFIG_C60802_SUPPORT
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/* c60802 regs reference */
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struct u2phy_reg_c *u2phy_regs_c;
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struct u3phya_reg_c *u3phya_regs_c;
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struct u3phya_da_reg_c *u3phya_da_regs_c;
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struct u3phyd_reg_c *u3phyd_regs_c;
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struct u3phyd_bank2_reg_c *u3phyd_bank2_regs_c;
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struct sifslv_chip_reg_c *sifslv_chip_regs_c;
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struct sifslv_fm_feg_c *sifslv_fm_regs_c;
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#endif
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#ifdef CONFIG_D60802_SUPPORT
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/* d60802 regs reference */
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struct u2phy_reg_d *u2phy_regs_d;
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struct u3phya_reg_d *u3phya_regs_d;
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struct u3phya_da_reg_d *u3phya_da_regs_d;
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struct u3phyd_reg_d *u3phyd_regs_d;
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struct u3phyd_bank2_reg_d *u3phyd_bank2_regs_d;
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struct sifslv_chip_reg_d *sifslv_chip_regs_d;
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struct sifslv_fm_feg_d *sifslv_fm_regs_d;
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#endif
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#ifdef CONFIG_E60802_SUPPORT
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/* e60802 regs reference */
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struct u2phy_reg_e *u2phy_regs_e;
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struct u3phya_reg_e *u3phya_regs_e;
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struct u3phya_da_reg_e *u3phya_da_regs_e;
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struct u3phyd_reg_e *u3phyd_regs_e;
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struct u3phyd_bank2_reg_e *u3phyd_bank2_regs_e;
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struct sifslv_chip_reg_e *sifslv_chip_regs_e;
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struct spllc_reg_e *spllc_regs_e;
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struct sifslv_fm_feg_e *sifslv_fm_regs_e;
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#endif
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#ifdef CONFIG_A60810_SUPPORT
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/* A60810 regs reference */
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struct u2phy_reg_a *u2phy_regs_a;
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struct u3phya_reg_a *u3phya_regs_a;
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struct u3phya_da_reg_a *u3phya_da_regs_a;
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struct u3phyd_reg_a *u3phyd_regs_a;
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struct u3phyd_bank2_reg_a *u3phyd_bank2_regs_a;
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struct sifslv_chip_reg_a *sifslv_chip_regs_a;
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struct spllc_reg_a *spllc_regs_a;
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struct sifslv_fm_reg_a *sifslv_fm_regs_a;
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#endif
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#endif
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};
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struct u3phy_operator {
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PHY_INT32(*init)(struct u3phy_info *info);
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PHY_INT32(*change_pipe_phase)(struct u3phy_info *info, PHY_INT32 phy_drv,
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PHY_INT32 pipe_phase);
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PHY_INT32(*eyescan_init)(struct u3phy_info *info);
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PHY_INT32(*eyescan)(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1,
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PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y,
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PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en,
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PHY_INT32 num_ignore_cnt);
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PHY_INT32(*u2_connect)(struct u3phy_info *info);
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PHY_INT32(*u2_disconnect)(struct u3phy_info *info);
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PHY_INT32(*u2_save_current_entry)(struct u3phy_info *info);
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PHY_INT32(*u2_save_current_recovery)(struct u3phy_info *info);
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PHY_INT32(*u2_slew_rate_calibration)(struct u3phy_info *info);
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};
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#undef EXTERN
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#ifdef U3_PHY_LIB
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#define EXTERN
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#else
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#define EXTERN \
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extern
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#endif
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EXTERN struct u3phy_info *u3phy;
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EXTERN struct u3phy_operator *u3phy_ops;
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/*********eye scan required*********/
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#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
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#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
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typedef enum {
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SCAN_UP,
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SCAN_DN
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} enumScanDir;
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struct strucScanRegion {
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PHY_INT8 bX_tl;
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PHY_INT8 bY_tl;
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PHY_INT8 bX_br;
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PHY_INT8 bY_br;
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PHY_INT8 bDeltaX;
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PHY_INT8 bDeltaY;
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};
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struct strucTestCycle {
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PHY_UINT16 wEyeCnt;
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PHY_INT8 bNumOfEyeCnt;
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PHY_INT8 bPICalEn;
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PHY_INT8 bNumOfIgnoreCnt;
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};
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#define ERRCNT_MAX 128
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#define CYCLE_COUNT_MAX 15
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/* / the map resolution is 128 x 128 pts */
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#define MAX_X 127
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#define MAX_Y 127
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#define MIN_X 0
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#define MIN_Y 0
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PHY_INT32 u3phy_init(void);
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EXTERN struct strucScanRegion _rEye1;
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EXTERN struct strucScanRegion _rEye2;
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EXTERN struct strucTestCycle _rTestCycle;
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EXTERN PHY_UINT8 _bXcurr;
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EXTERN PHY_UINT8 _bYcurr;
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EXTERN enumScanDir _eScanDir;
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EXTERN PHY_INT8 _fgXChged;
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EXTERN unsigned int _bPIResult;
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/* Comment for saving the kernel size. This's only used at external PHY*/
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#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
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EXTERN PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
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EXTERN PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
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#endif
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extern void phy_hsrx_set(void);
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/***********************************/
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#ifndef CONFIG_PHY_MTK_SSUSB
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extern void __iomem *ap_uart0_base;
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extern void __iomem *ap_pll_con0;
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#endif
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#ifdef CONFIG_FPGA_EARLY_PORTING
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extern void __iomem *i2c1_base;
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#endif
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#ifndef CONFIG_PHY_MTK_SSUSB
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enum {
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USB_DPIDLE_ALLOWED = 0,
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USB_DPIDLE_FORBIDDEN,
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USB_DPIDLE_SRAM,
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USB_DPIDLE_TIMER
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};
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#ifdef CONFIG_PROJECT_PHY
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extern void enable_ipsleep_wakeup(void);
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extern void disable_ipsleep_wakeup(void);
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extern void usb_hal_dpidle_request(int mode);
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#else
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static inline void usb_hal_dpidle_request(int mode) {};
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static inline void enable_ipsleep_wakeup(void) { };
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static inline void disable_ipsleep_wakeup(void) { };
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#endif
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#endif
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/***********************************/
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#endif
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